參數(shù)資料
型號: DS21554LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 67/117頁
文件大?。?/td> 698K
代理商: DS21554LN
DS21354 & DS21554
53 of 117
One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no
restrictions on which channels can be looped back or on how many channels can be looped back.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per–Channel Loopback]
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1 (26)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2 (27)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3 (28)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TIR4 (29)
SYMBOLS POSITIONS NAME AND DESCRIPTION
CH1 - 32
TIR1.0 - 4.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR3.5 = 1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 3-1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION NAME AND DESCRIPTION
TIDR7
TIDR.7
MSB of the Idle Code (this bit is transmitted first)
TIDR0
TIDR.0
LSB of the Idle Code (this bit is transmitted last)
11.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 32 E1 channels.
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel one is shown; see for other register address)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
TC1 (60)
SYMBOL
POSITION NAME AND DESCRIPTION
C7
TC1.7
MSB of the Code (this bit is transmitted first)
C0
TC1.0
LSB of the Code (this bit is transmitted last)
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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