參數(shù)資料
型號(hào)： DS21554LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Interface
英文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 42/117頁
文件大小： 698K
代理商： DS21554LN
DS21354 & DS21554
30 of 117
The Test registers at addresses 09, 15, 19, and AC hex are used by the factory in testing the
DS21354/554. On power-up, the Test registers should be set to 00h in order for the DS21354/554 to
operate properly.
6.1 Power–Up Sequence
On power–up, after the supplies are stable the DS21354/554 should be configured for operation by
writing to all of the internal registers (this includes setting the Test Registers to 00h) since the contents of
the internal registers cannot be predicted on power–up. The LIRST (CCR5.7) should be toggled from
zero to one to reset the line interface circuitry (it will take the device about 40ms to recover from the
LIRST bit being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bits
(CCR6.0 & CCR6.1) should be toggled from a zero to a one (this step can be skipped if the elastic stores
are disabled).
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
Bit 6
Bit 5
Bit 4
ID3
ID2
ID1
ID0
SYMBOL
POSITION NAME AND DESCRIPTION
T1E1
IDR.7
T1 or E1 Chip Determination Bit. Set to 1.
0=T1 chip
1=E1 chip
Bit 6
IDR.6
Bit 6. See Table 6-1
Bit 5
IDR.5
Bit 5. See Table 6-1
Bit 4
IDR.4
Bit 4. See Table 6-1
ID3
IDR.3
Chip Revision Bit 3. MSB of a decimal code that represents the chip
revision.
ID2
IDR.1
Chip Revision Bit 2.
ID1
IDR.2
Chip Revision Bit 1.
ID0
IDR.0
Chip Revision Bit 0. LSB of a decimal code that represents the chip
revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
–
FRC
SYNCE
RESYNC
SYMBOL
POSITION NAME AND DESCRIPTION
RSMF
RCR1.7
RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSM
RCR1.6
RSYNC Mode Select.
0 = frame mode (see the timing in Section 19-1)
1 = multiframe mode (see the timing in Section 19-1)
RSIO
RCR1.5
RSYNC I/O Select. (note: this bit must be set to zero when RCR2.1=0).
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
–
RCR1.4
Not Assigned. Should be set to zero when written.
相關(guān)PDF資料
PDF描述
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
DS21602N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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