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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 90/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
18
Datasheet
BGACK*
12
I/O (OD)
BUS GRANT ACKNOWLEDGE*: As an input, this signal is used to determine if
another alternate bus master is in control of the bus. As an output, it signals to
other bus masters that this device is in control of the bus.
BERR*
100
I
BUS ERROR*: If this input becomes active while the CD2431 is a bus master,
the current bus cycle is terminated, the bus relinquished, and an interrupt
generated to indicate the error to the host processor.
A[7:0]
71–78
I/O (TS)
ADDRESS [0–7]: When the CD2431 is not a bus master, these pins are inputs
used to determine which registers are being accessed, or which interrupt is
being acknowledged. When ADLD* is low, A[0–7] output address bits 8 through
15 for external latching. When the CD2431 is a bus master, A[0–7] output the
least-significant byte of the transfer address.
A/D[15:0]
80, 81, 83,
84, 86–95,
97, 98
I/O (TS)
ADDRESS/DATA [0–15]: When the CD2431 is not a bus master, these pins
provide the 16-bit data bus for reading and writing to the CD2431 registers.
When ADLD* is low, A/D[0–15] provide the upper address bits for external
latching. When the CD2431 is a bus master, A/D[0–15] provide a multiplexed
address/data bus for reading and writing to system memory.
ADLD*
29
O (TS)
ADDRESS LOAD*: This is a strobe used to externally latch the upper portion of
the system address bus A[8–31]. While ADLD* is low, address bits 16–31 are
available on A/D[0–15], and address bits 8 through 15 on A[0–7].
AEN*
30
O (TS)
ADDRESS ENABLE*: This output is used to output enable the external
address bus drivers during CD2431 DMA cycles.
DATEN*
28
O (TS)
DATA ENABLE*: This output is active when either the CD2431 is a bus master,
or the CS* and DS* pins are low. It is used to enable the external data bus
buffers during host register read/write operations or during DMA operations. For
operations on 32-bit buses, this signal needs to be gated with A[1] to select the
correct half of the data bus.
DATDIR*
27
O (TS)
DATA DIRECTION*: This output is active when either the CD2431 is a bus
master, or the CS* pin is low. It is used to control the external data buffers; when
low, the buffers should be enabled in the CD2431 to system bus direction.
CLK
5
I
CLOCK: System clock.
BUSCLK
6
O
BUS CLOCK: This is the system clock divided by 2, which is used internally to
control certain bus operations. This pin is driven low during hardware reset.
RESET*
26
I
RESET*: This signal should stay valid for a minimum of 20 ns. The reset state
of the CD2431 is guaranteed at the rising edge of this signal. When RESET* is
removed, the CD2431 also performs a software initialization of its registers.
TEST
33
I
TEST: In normal operation, this pin should be kept low. For board-level testing
purposes, it provides a mechanism for forcing normal output pins to High-
Impedance mode. When the TEST pin is high, the following pins are in High-
Impedance mode: BUSCLK, BGOUT*, IACKOUT*, RXCOUT[0–1], RTS*[0–1],
DTR*[0–1], and TXD[0–1].
To ensure all CD2431 outputs are high-impedance, either of the following two
conditions must be met: the RESET* pin can be driven low, and the TEST pin
driven high; or, the CD2431 is kept in the bus idle state (not accessed for read/
write operations nor DMA active), and the TEST pin is driven high.
RTS*[0–3]
56, 60, 65,
69
O
REQUEST TO SEND* [0–3]: This output can be controlled automatically by the
CD2431 to indicate that data is being sent on the TXD pin.
Table 1.
Pin Descriptions (Sheet 2 of 3)
Symbol
Pin
Number
Type
Description
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