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| 型號(hào)： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁(yè)數(shù)： | 134/186頁(yè) |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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Advanced Multi-Protocol Communications Controller — CD2431
Datasheet
51
Receiver A and B Buffers
In the Figure 8, buffers A and B are contained in RAM external to the CD2431. All others
(DMABSTS, ARBADR, ARBCNT, ARBSTS, RCBADR, BRBADR, BRBCNT, and BRBSTS)
are inside the CD2431.
Example 1
Receive a frame from channel 1 — no chaining.
1. The host must first make a receive buffer available before a frame can be received. Thus, the
host checks the Nrbuf bit (DMABSTS[1]) for channel 1 to determine which buffer is next. In
this example, Nrbuf is set to ‘0’ indicating that buffer A is used next.
2. The host sets up the starting address — ARBADR, and the buffer byte count — ARBCNT.
When the host writes the count — ARBCNT, the host has defined the size limit for the buffer.
3. The host then gives the buffer to the CD2431 by setting the 2431own bit in the ARBSTS status
register. This notifies the CD2431 that it is now OK to write received.
4. The Rbusy bit in the DMABSTS register for channel 1 is ‘0’ until a frame starts to be received.
When frame data starts coming in, the CD2431 sets Nrbuf to notify the host that buffer B is
next. As data bytes are written into the buffer, the current buffer pointer (RCBADR) is updated
by the CD2431.
5. At the end of the received frame, the CD2431 tests for correct end of frame delimiter and
CRC. When the received frame is complete, the CD2431 clears the Rbusy bit. In this example,
there is no receive chaining, so the received frame byte count is less than or equal to the buffer
size count — ARBCNT. The CD2431 writes the value of the actual received byte count into
the same register — ARBCNT. (Note that the host has written the maximum buffer size in
ARBCNT when the buffer is given to the CD2431; however, when the buffer is returned back
to the host, the CD2431 has written the actual byte count of the received buffer into
ARBCNT.)
Figure 8. Receiver A and B Buffers
CD2431 Transmit
DMA Registers
Physical
Receiver
Buffer
A
Receiver
Buffer
B
ARBADR (32)
ARBCNT (16)
ARBSTS (8)
(Status register)
RCBADR (32)
(Currently using Buffer A)
BRBADR (32)
BRBCNT (16)
BRBSTS (8)
(Status register)
Starting Address
Buffer Byte Count
Current Address
Starting Address
Buffer Byte Count
NOTE: Number of bits in each register is shown in parentheses ( ).
Buffer A and buffer B do not need to be the same length.
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