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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 122/186頁 |
| 文件大小： | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
40
Datasheet
Transmit Interrupt register
Lowest priority: Modem Interrupt register
5.2.4.2
Systems with Interrupt Controllers
Some systems use an interrupt controller that supplies its own vector during the interrupt
acknowledge cycle. To function properly, the CD2431 needs an IACK cycle in response to its
interrupt request . These systems can decode three distinct locations from the CD2431 to produce
an IACKIN* instead of CS*. The PILR registers should be programmed with the addresses of these
three locations.
Alternatively, a single location can be decoded and the three PILRs given identical values as
described earlier. In either case, the host should read one of these locations before the first access to
the device in an interrupt service routine. The CD2431 enters its interrupt acknowledge context for
the proper type and channel, and the data returned is the device interrupt vector from the LIVR.
5.2.5
Multi–CD2431 Systems
Multiple CD2431s can be chained for systems requiring more than four channels. Each group of
interrupt request lines (IREQn*) can be connected in a parallel wired-OR fashion. The system
Interrupt Acknowledge signal is connected to the IACKIN* pin of the first device, its IACKOUT*
is then connected to the IACKIN* of the next device, and so on, forming a chain of CD2431s.
5.2.5.1
Keep and Pass Logic
The acceptance of an interrupt acknowledge cycle by the CD2431 depends on whether the part is
requesting service and whether the least-significant seven address bits match the contents of the
appropriate PILR. The following rules apply to the keep-and-pass logic:
1. If the CD2431 does not have an interrupt asserted, the interrupt acknowledge is passed out on
IACKOUT*.
2. If the CD2431 is asserting one or more of its interrupts, but the interrupt priority levels driven
on the address bus by the host do not match the contents of the appropriate PILR, this interrupt
acknowledge is also passed out on the IACKOUT*.
3. If the CD2431 is asserting an interrupt and the interrupt priority level on the address bus
matches the PILR for that interrupt type, the interrupt acknowledge is accepted by the
CD2431, and the vector from the LIVR is driven onto the data bus.
5.2.5.2
Fair Share Scheme
When multiple CD2431s are chained, the Fair Share logic in these devices guarantees that the
interrupts from all CD2431s in the system are presented to the host with equal urgency. There is no
positional hierarchy in the interrupt scheme. For example, the CD2431 that is farthest from the host
has an equal chance of getting its interrupts through as the CD2431 that is nearest to the top of the
interrupt chain. The Fair Share scheme is totally transparent to the user, and no enabling or
disabling is required.
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