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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 123/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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Advanced Multi-Protocol Communications Controller — CD2431
Datasheet
41
When an interrupt request line is asserted, the Fair bit for that type of interrupt on the asserting
device is cleared. The Fair bit remains cleared until the interrupt line returns to a high state. The
CD2431 does not assert a new interrupt of that type while the corresponding Fair bit is cleared.
Therefore, when multiple CD2431s assert interrupts together, each one is serviced in turn, before
they can reassert the same interrupt type.
The IREQn* lines are open-drain outputs that can be tied together in groups of the same type,
creating a Fair Share scheme for each group of interrupts. Alternatively, all three groups can be tied
to a common request using the CD2431 internal-priority scheme (see Section 5.2.4.1).
5.3
FIFO and Timer Operations
Each channel in the CD2431 has a 16-byte receive FIFO and a 16-byte transmit FIFO. The FIFOs
are accessible through the RDR and TDR. These Virtual registers are shared among the four
channels; therefore, they can not be accessed outside an interrupt context.
Each channel’s threshold level is common for both FIFOs. It is set by COR4 (Channel Option
Register 4), with a maximum threshold value of 12. The FIFO threshold is meaningful in both
DMA and non-DMA modes. In DMA mode, the FIFO threshold determines when transfer bursts
should occur. In non-DMA mode, the threshold level determines when transfer interrupts are
asserted.
5.3.1
Receive FIFO Operation
In the Asynchronous mode, a Good Data interrupt is initiated when the number of characters in the
FIFO is greater than the FIFO threshold. Note that receive timeout and receive data exception
conditions also cause an interrupt to the host.
In Synchronous mode, an interrupt request for data transfer is initiated when the number of
characters is greater than the FIFO threshold or an end of frame is reached.
5.3.2
Transmit FIFO Operation
The TxDat and TxEmpty bits in the IER control the generation of transmit FIFO interrupts. The
CD2431 initiates an interrupt request for more data when the number of empty bytes in the FIFO is
greater than the threshold set. During synchronous operation when the last byte of the frame is
transferred to the FIFO, the CD2431 stops asserting transmit interrupts until the frame is sent.
5.3.3
Timers
The global TPR (Timer Period register) provides a timer prescale ‘tick’ as a clock source for the
timers. The TPR counter is clocked by the system clock (CLK) divided by 2048. To maintain timer
accuracy, the TPR should not be programmed with a value less than 16 (10 hex) — a ‘tick’ of about
1 millisecond when CLK is 33 MHz.
Each channel has two timers: one 16-bit general timer 1 (GT1), and one 8-bit general timer 2
(GT2). Their operation and programming are different in synchronous and asynchronous protocols.
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