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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 152/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
68
Datasheet
When end-of-frame status is passed to the CD2431 by the TEOIR or the A/BTBSTS, and the
remaining data transmitted, the CRC and a closing flag are appended to the frame. If a new frame is
available immediately, the correct number of opening flags are transmitted and data transmission
starts. If data is not available, the line is returned to its idle condition.
If data underrun occurs, the CD2431 does not append a CRC, but aborts the transmission by
sending eight continuous ‘1’s, and then reverts to the idle condition. An underrun interrupt is
generated, and if interrupt transfer is being used, the CPU should provide an EOF response in
TEOIR. If DMA Transfer mode is being used, the CD2431 discards DMA buffers until an EOF
buffer is found; transmission then resumes from the next buffer. This ensures correct operation
when a multiple buffer frame underruns.
When programmed in NRZI mode and idle in Mark mode, after the closing flag and the first eight
‘1’s are transmitted, the transmit data line is sampled to determine if it is a logic high or low. If it is
low, an extra ‘0’ is transmitted to force the line to be a logic high.
When idle in Flag mode is selected, the send pad and opening number of flags have no
significance; transmission is started when data is first made available in the FIFO. If no data
underrun occurs, the frame is terminated normally with a CRC, and then continuous flags are
generated. If an underrun does occur, then no CRC is appended, eight ‘1’s are transmitted, and then
continuous flags and an underrun interrupt are generated.
6.1.3
HDLC Receive Mode
When enabled, the receiver enters Flag Hunt mode. When the first flag is detected, the next non-
flag/abort character is treated as the start of frame. If no address recognition is enabled, frame
reception then continues; if Address Recognition mode is enabled, the incoming data is compared
with the receive address registers. The following two modes of address recognition are available:
First byte of address field only (four possible matches available against RFAR1–4).
First and second byte address field (two possible matches available against RFAR1–2,
RFAR3– 4).
For the purposes of address matching, the Address Extension bit is not interpreted by the device.
The address matching occurs on either the complete first byte, or the complete first and second byte
of the frame. If no address match is recognized, Flag Hunt mode is once again entered, thereby
discarding the current frame. If a match is found, normal frame reception continues. When the
closing flag of the frame is detected, the data remaining in the FIFO is passed to the CPU, either
through DMA transfers or Good Data interrupts, and then an EOF (end of frame) interrupt is
generated. The CRC can be either validated or ignored. If the CD2431 does not check the CRC, it
is passed onto the host. A validated CRC can be discarded or passed onto the host for diagnostic
purposes.
The next non-flag/abort character restarts the process; the current state of the receive process is
visible to the CPU by the CSR register, which indicates whether data, flag, or mark are currently
being received. To support the data phase of an X.21 connection, a clear detect feature can be
enabled by COR1. When enabled, the receive data and CTS* pin are monitored for the clear
indication (0, off) from the remote. If detected, the remainder of the current frame is discarded, and
a clear detect indication is passed to the CPU by the RISR. However, the channel remains in HDLC
mode until modified by the CPU.
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