- 您現在的位置：買賣IC網 > PDF目錄98079 > SCD243110QCD (INTEL CORP) 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 PDF資料下載
參數資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數： | 128/186頁 |
| 文件大小： | 2204K |
| 代理商： | SCD243110QCD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁當前第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁
CD2431 — Advanced Multi-Protocol Communications Controller
46
Datasheet
The CD2431 keeps track of which buffer (A or B) is to be used next in the status bits — Ntbuf for
transmit and Nrbuf for receive. The relationship between the 2431own bit and the ‘next’ bits is
shown later. The receive buffers are handled in the same way using the Nrbuf (next receive buffer).
Chaining is used to break up relatively long frames into shorter blocks in memory, and is useful
where there are frequent smaller frames and occasional long frames. Chaining allows more
efficient use of the user RAM.
The EOF Status bit controls chaining in Synchronous modes. Chaining applies to both transmit and
receive. For transmit, the host determines the EOF bit; for receive, the CD2431 determines the
EOF bit.
In Transmit DMA when the first buffer is supplied to the CD2431, it is treated as the start of frame
— the CRC is reset and leading pad/flag/syn characters are transmitted, followed by the data. If the
EOF bit is set, the CRC and closing flag/syn is appended, and the next buffer is again treated as the
start of frame. If the EOF bit is not set, the CD2431 treats the buffer as the first part of a larger
frame and chains into the next buffer (does not reset CRC); this process continues until a buffer is
supplied with the EOF bit set.
5.4.5
Transmit DMA Transfer
As in receive data transfers, two buffers are available for DMA transmit transfers. The A/
BTBADR
and A/BTBCNT (Transmit Buffer Address and Transmit Buffer Count registers)
contain the start address of and the byte count in the buffers. These registers are set by the host
when initiating a transfer. The CD2431 makes a copy of the registers to perform the transfer,
leaving the originals unchanged. The transfer of buffers between the host and the CD2431 is
controlled by the A/BTBSTS (Transmit Buffer Status) registers.
Buffers can contain either complete frames or blocks of data, linked together to form a complete
frame or a block, or used in an Append mode to transmit data as it arrives from another process.
The first two transfer types are Block mode transfers, the last is the Append mode, and both are
described later. The management of the buffers reduces the processor overhead associated with
short data transfers and increases the minimum response time requirements for frame-based
transmissions.
Table 3.
A and B Buffers and Chaining
Ntbuf
2431own
Buffer A
2431own
Buffer B
Transmit Action
0
Send nothing
0
1
0
Host sets up buffer A
1
0
CD2431 accepts buffer A and marks B as next
1
0
CD2431 completes A Tx, and passes it to host
1
0
1
Host sets up buffer B
0
1
CD2431 accepts B and marks A as next
0
1
Host sets up buffer A
11
0
CD2431 completes B Tx, passes to host, accepts A and
marks B as next
1
0
CD2431 completes A Tx and passes it to host
. A/B is used as a Buffer register abbreviation indicating A buffer / B buffer followed by the register acronym.
相關PDF資料 |
PDF描述 |
|---|---|
| SCG2500AI-019.44M | 51.84 MHz, OTHER CLOCK GENERATOR, DSO14 |
| SCG4525 | 4000/14000/40000 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), DSO18 |
| SCN2641CC1A28 | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC28 |
| SCN2681TC1A44A | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| SCN68562C2N48 | 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PDIP48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SCD248110QCD | 功能描述:IC 4CH WAN COMMUN CTRL 100QFP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| SCD24H | 制造商:ZOWIE 制造商全稱:Zowie Technology Corporation 功能描述:Schottky Barrier Diode |
| SCD24L | 制造商:ZOWIE 制造商全稱:Zowie Technology Corporation 功能描述:SURFACE MOUNT LOW VF SCHOTTKY BARRIER RECTIFIER |
| SCD24LH | 制造商:ZOWIE 制造商全稱:Zowie Technology Corporation 功能描述:Schottky Barrier Diode |
| SCD255K851A3L28-A | 制造商:Cornell Dubilier Electronics 功能描述:CAPACITOR PP MODULE, 2.5UF, 850V, Product Range:CORNELL DUBILIER - SCD Series, C 制造商:Cornell Dubilier Electronics 功能描述:FILM CAPACITOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。