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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 79/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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Advanced Multi-Protocol Communications Controller — CD2431
Datasheet
17
Table 1.
Pin Descriptions (Sheet 1 of 3)
Symbol
Pin
Number
Type
Description
CS*
1
I
CHIP SELECT*: When low, the CD2431 registers can be read or written by the
host processor.
AS*
14
I/O (TS)
ADDRESS STROBE*: When the CD2431 is a bus master, this pin is an output
that indicates that R/W*, A[0–7], and the externally latched A[8–31] are valid.
DS*
15
I/O (TS)
DATA STROBE*: When the CD2431 is not a bus master, this is an input used to
strobe data into registers during write cycles and enable data onto the bus
during read cycles. When the CD2431 is a bus master, DS* is an output used to
control data transfer to and from system memory.
R/W*
13
I/O (TS)
READ/WRITE*: When the CD2431 is not a bus master, this pin is an input that
determines if a read or write operation is required when the CS* and DS*
signals are active. When the CD2431 is a bus master, R/W* is an output and
indicates whether a read from or a write to system memory is being performed.
DTACK*
16
I/O (OD)
DATA TRANSFER ACKNOWLEDGE*: When the CD2431 is not a bus master,
this is an output and indicates to the host when a read or write to the CD2431 is
complete. When BR* is driven low by the CD2431, DTACK* is an input that
indicates that the system bus is no longer in use. When the CD2431 is a bus
master, DTACK* is an input that indicates when system memory read and write
cycles are complete.
SIZ[0–1]
3, 4
I/O (TS)
SIZE [0–1]: When not the active bus master, these are inputs that determine the
size of the operand being read or written by the host.
SIZ[1] SIZ[0]
01
Byte
1
0
16 Bit
0
32 Bit
11
3 Bytes
When the CD2431 is a bus master, this is an output determining the size of the
operand being transferred to or from system memory.
SIZ[1] SIZ[0]
01
Byte
1
0
16 Bit
See BYTESWAP description.
The CD2431 drives DTACK* even though the device does not respond to
such byte alignment.
IACKIN*
17
I
INTERRUPT ACKNOWLEDGE IN*: This input qualified with DS*, and A[0–6],
acknowledges CD2431 interrupts.
IACKOUT*
19
O
INTERRUPT ACKNOWLEDGE OUT*: This output is driven low during interrupt
acknowledge cycles for which no internal interrupt is valid.
IREQ*[1–3]
21, 23, 24
I/O (OD)
INTERRUPT REQUEST* [1–3]: These outputs signal that the CD2431 has a
valid interrupt for modem-lead activity (IREQ*[1]), transmit activity (IREQ*[2]), or
receive activity (IREQ*[3]).
BR*
7
OD
BUS REQUEST*: This output is used to signal to the (open drain) host
processor or bus arbiter that bus mastership is required by the CD2431.
BGIN*
9
I
BUS GRANT IN*: This input indicates that the bus is available after the current
bus master relinquishes the bus.
BGOUT*
10
O
BUS GRANT OUT*: This output is asserted when BGIN* is low and no internal
Bus Request has been made. A daisy-chain scheme of bus arbitration can be
formed by connecting BGOUT* to BGIN* of the next device in the chain. If a
priority scheme is preferred, bus requests must be prioritized externally and bus
grant routed to the BGIN* of the appropriate device
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