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| 型號(hào)： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁(yè)數(shù)： | 1/186頁(yè) |
| 文件大小： | 2204K |
| 代理商： | SCD243110QCD |
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CD2431
Advanced Multi-Protocol Communications Controller
Datasheet
The CD2431 is a 4-channel synchronous/asynchronous communications controller specifically
designed to reduce host-system processing overhead and increase efficiency in a wide variety of
communications applications. The CD2431 is packaged in a 100-pin MQFP, and offers eight
clock/modem pins per channel. The device has four fully independent serial channels that
support asynchronous, asynchronous-HDLC, and bit-synchronous (HDLC/SDLC) protocols.
The CD2431 is based on a proprietary on-chip RISC processor that performs all time-critical,
low-level tasks that are otherwise performed by the host system.
The CD2431 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored
interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and-
forget’ transmit support — the host need only inform the CD2431 of the location of the packet to
be sent. Similarly, on receive, the CD2431 automatically receives a complete packet with no host
intervention or assistance required. The DMA controller also has an ‘Append mode’ for use in
asynchronous applications.
The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer
schemes. Each channel and direction has two active buffers.
The CD2431 can be programmed to interrupt the host at the completion of a frame or buffer. In
applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames
to be divided into multiple buffers.
For applications where a DMA interface is not desired, the device can be operated as an
interrupt-driven or polled device. This choice is available individually for each channel and each
direction. For example, a channel can be programmed for DMA transmit and interrupt-driven
receive.
In either case, 16-byte FIFOs on each channel and in each direction reduce latency time
requirements, making both software and hardware designs less time-critical. Threshold levels on
FIFOs are user-programmable.
Efficient vectored interrupts are another way the CD2431 help system efficiency. Separate
interrupts are generated for transmit, receive, and modem-signal change, with unique user-
defined vectors for each type and channel. This allows very flexible interfacing and fast,
efficient interrupt coding. For example, the Good Data
interrupt allows the host to vector
directly to a routine that transfers the data — no status or error checking is required.
As of May 2001, this document replaces the Basis Communications
Corp. document CL-CD2431 — Advanced Multi-Protocol Communications Controller.
May 2001
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