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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 139/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
56
Datasheet
The CPU has the following five options:
1. Terminate the buffer.
2. Discard the exception.
3. Terminate the buffer and discard the exception.
4. Continue from the current position in the buffer.
5. Leave an ‘n’-byte gap in the buffer and then continue.
The required option is written to the REOIR by the CPU to terminate the interrupt. If
the terminate buffer option is chosen, the 2431own bit in the A/BRBSTS register
should first be cleared by the CPU, or a new buffer can be supplied by the CPU.
5.4.9.1
Receive Timeout in Asynchronous DMA Mode
In Asynchronous DMA mode, the only way that the CD2431 releases the ownership is by reaching
the end-of-buffer. Receive timeouts or any exceptions do not release the ownership if end-of-buffer
condition is not met. The following illustrates recommended procedures to handle a receive
timeout in Asynchronous DMA mode.
Scenario 1: Buffer A is currently selected, receive timeout occurs, host wants to continue on.
Recommendation: Do nothing in the receive timeout interrupt service routine.
Scenario 2: Buffer A is currently selected, receive timeout occurs, host no longer requires DMA.
Recommendation: Reset ownership bits in ARBSTS/BRBSTS, and set TermBuff in REOIR in the
receive timeout interrupt service routine.
Scenario 3: Buffer A is currently used, a receive timeout occurs, host wants to start DMA in buffer
B.
Recommendation: Set TermBuff in REOIR in the receive timeout interrupt service routine. The
CD2431 switches to buffer B.
Note:
When a receive timeout occurs in buffer B, the CD2431 pops back to buffer A, unless the host
clears both Ownership Status bits.
The above scenarios applies if buffer B is selected first.
5.4.9.2
Receive Bus Errors
When a receive bus error interrupt is generated, the RISR and A/BRBSTS registers both indicate a
bus error status. The current transfer address is available in the RCBADR[0–3] registers, the bus
error occurred on the last transfer that started at this address. This means that the actual error
address can be up to 16 bytes further in the buffer.
Following a bus-error condition, the CPU can either discontinue the current buffer or retry from the
start of the last transfer. If the buffer is discontinued, the number of valid receive bytes can be
calculated by subtracting the starting address A/BRBADR[0–3] from the current address
RCBADR[0–3]. The CPU should set the TermBuff bit in REOIR to terminate this buffer and move
to the next.
The transfer that failed to the first buffer (due to the bus error) is still in the receive FIFO and is
transferred to the next buffer following the end of the interrupt.
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