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參數(shù)資料
| 型號(hào)： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 124/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
42
Datasheet
5.3.4
Timers in Synchronous Protocols
In synchronous protocols, the timers have no special significance for the CD2431; they are
available to support the protocols. They are started by host commands or by interrupts generated by
the CD2431. General timers 1 and 2 can be started in either of two ways:
1. By loading a new value to GT1 or GT2 when the timer is not running.
2. By setting the SetTm1 or SetTm2 bits in the EOIR when terminating an interrupt service
routine. In this case, the value should be written to the appropriate Interrupt Status register
(RISR, TISR, or MISR).
These timers can be disabled by a command through the CCR (Channel Command register).
5.3.5
Timers in Asynchronous Protocols
The receive timer is restarted from the value programmed in RTPR every time a character is
received and loaded into the FIFO, or data is read by the host. For example, receive FIFO threshold
is set to eight, and six characters are stored in the receive FIFO. If no more characters are received
and the receiver timer times-out, a receive interrupt is asserted (in DMA mode, DMA transfer
occurs). The host is expected to retrieve all six characters from the receive FIFO. Assuming the
host is still enabling this feature (that is, IER[5] is still set) and if there is no character being
received and receiver timer times-out, a receive exception timeout interrupt (a group 3 interrupt) is
asserted. The timer can be disabled if the value in RTPR is set to ‘0’ or the RET bit (IER[5]) is
cleared.
5.3.6
Transmit Timer
The TTR (Transmit Timer register) is used only if the embedded transmit command is enabled in
the COR2. The delay transmit command specifies the delay period loaded in the TTR; no further
transmit operations are performed until this timer reaches zero. The current state of the line is held
at either ‘0’ for send break or ‘1’ for inter-character fill.
5.4
DMA Operation
The CD2431 uses a simple, but powerful, double-buffering method that is readily compatible with
higher-level buffer control procedures, such as circular queues, link lists, and buffer pools. Each
transmitter and receiver is assigned an ‘A’ and ‘B’ buffer. When transmitting, the host processor
alternately fills the A and B buffers and commands the CD2431 to transmit the buffers one at a
time. When receiving, the CD2431 fills the A and B buffers and informs the host processor when
each is ready.
A simple Ownership Status bit is used for each buffer; this ensures that there are no deadlocks
between the host and the CD2431 regarding the use of a particular buffer.
By using the simple and flexible DMA management of the CD2431, the user host processor is
concerned with transmit/receive data on a block-by-block -basis. The user does not need to be
concerned with character-by-character transfers, or even filling and emptying the FIFOs. DMA
controls are user-selectable per-channel and operate independently of one another.
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