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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 138/186頁 |
| 文件大小： | 2204K |
| 代理商： | SCD243110QCD |
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Advanced Multi-Protocol Communications Controller — CD2431
Datasheet
55
5.4.8.3
Append Mode
The Append mode reduces the CPU overhead required to provide asynchronous terminal echoing
functionality; this is also necessary for any similar application that involves an unpredictable
datastream. The A buffer can be set into Append mode by the ATBSTS register. This buffer can
then be used for the echoed data, while the B buffer is used for all other output data. The append
buffer allows data transmission to start from a buffer before all the data is available for
transmission. For example, terminal echoing requires that each character is echoed (or translated
and echoed) before the complete line is typed.
To operate in Append mode, the ATBADR and ATBCNT are set as normal (the ATBCNT can be
zero), and the 2431own and Append bits are set in the ATBSTS. When any data is available for
transmission, it is placed in the RAM buffer by the CPU, and the total buffer byte count is updated
in the ATBCNT. The CD2431 now scans the ATBCNT register for any changes; if new data is
found, it is read from the buffer and transmitted.
When no more data is found in the append buffer, the CD2431 scans the B buffer for ownership. If
the B buffer is owned by the CD2431, the data in that buffer is transmitted uninterrupted; at the end
of the transmission, the A buffer count continues to be scanned for new data.
For correct operation of this feature, the ATBCNT register should be updated with a word-write
operation. If only byte access is possible, the value should not exceed 256 bytes. This mode allows
multiple transfers to be performed through a single buffer; it saves CPU overhead by either
processing multiple buffers or in handling interrupts with every character.
Line retransmission becomes as simple as ‘stepping back’ in the buffer and resending. To terminate
the Append mode, a command can be given by the STCR to terminate the A buffer when all current
data has been sent.
5.4.8.4
Transmit Bus Errors
When a transmit bus error interrupt is generated, the TISR and A/BTBSTS registers both indicate a
bus error status. The current transfer address is available in the TCBADR[0–3] registers, and the
bus error occurred on the last transfer that started at this address. This means the actual error
address can be up to 16 bytes further in the buffer.
Following a bus error condition, the CPU can either discontinue the current buffer or retry from the
start of the last transfer. To discontinue, the current buffer and the TermBuff bit should be set when
TEOIR is written to at the end of the interrupt. In Synchronous mode, the frame is still in progress
and needs to be aborted by the STCR.
To retry the frame, the CPU should set the 2431own bit in the A/BTBSTS register, and not set the
TermBuff bit when writing to TEOIR at the end of the interrupt. This causes the last transfer to be
retried; should a bus error occur again, the above procedure is repeated. The CPU should check to
ensure that a bad location is not continually retried.
5.4.9
Receive Buffer Interrupts
When a receive buffer is complete, the CD2431 generates an end-of-frame receive exception
interrupt. It provides the CPU with RISR status and information on which buffer is complete.
When a receive error occurs, the device stops DMA at the point of error and generates a bus error
receive exception interrupt. RISR indicates the cause of the exception, and RCBADR provides the
next location in the receive buffer.
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