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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 133/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
50
Datasheet
15. When the CD2431 completes transmission, any necessary CRCs and ending frame delimiters
are transmitted.
16. The CD2431 optionally interrupts the host with EOF and EOB bits set (TISR[6:5]) to indicate
that the transmission has completed, and that this was the last link in the chain.
5.4.7
Receive DMA Transfer
In all protocol modes, two host memory buffers can be made available to each receive channel, by
the A/BRBADR and A/BRBCNT (Receive Buffer Address and Receive Buffer Count registers)
registers. To make a buffer available, the user must supply the buffer address in the Receive Buffer
Address registers; the number of free bytes in the buffer must be written in the Receive Buffer
Count registers, and the buffer status must be updated in the A/BRBSTS registers. The CD2431 is
then free to use the buffer for receive data, and updates the Buffer Status register as appropriate.
When the buffer is no longer in use, the CD2431 writes the number of bytes stored in the buffer in
RBCNT and updates status in RBSTS. This frees the host to take control of this buffer and supply a
new buffer in its place. The CD2431 automatically switches to the other buffer whenever one
buffer becomes full, or the end of a frame has been reached. If the other buffer has not been
allocated, the host still has the time required to fill the CD2431 16-byte FIFO, to respond, and to
avoid loss of data.
Special actions are taken depending on the channel protocol. In HDLC, PPP, SLIP, and MNP 4 the
end-of-frame/data block boundaries are recognized by the CD2431. When a data-block boundary is
detected, the current buffer is automatically terminated. If the other buffer is allocated and owned
by the CD2431, it becomes the current buffer. End-of-frame and block interrupts are also generated
to the host.
In Asynchronous mode, a host interrupt is generated when there are receive exceptions (framing
error, special character, and so on) but the buffer is not terminated. The data and exception status
are made available to the host, just as when the Asynchronous mode is purely interrupt-driven.
New data is buffered internally in the FIFO until the host services the exception interrupt. The host
has the following three options when terminating an exception interrupt:
1. The exception character can be discarded.
2. The buffer can be terminated if there is no additional interrupt to be generated. The transfer
count is not provided in A/BRBCNT, but can be calculated by RCBADR.
3. A user-defined gap can be left in the buffer.
These selections are communicated to the CD2431 by the value written by the host to the REOIR,
when the Receive Interrupt service is complete. Leaving an ‘n’ byte gap enables the host to insert
status of its own in the current buffer, while continuing to receive data in the same buffer. This
eliminates the overhead of allocating a new buffer. The host must have noted the starting location
of the gap while in the exception interrupt. This is done by reading the RCBADR. The address in
this register is guaranteed to be stable during the Receive Interrupt, and point to the next free
character location in the current DMA buffer. If the size of the gap supplied by the host is sufficient
to fill or complete the current buffer, the CD2431 automatically switches to the other buffer and
advances the Receive Current Buffer Address enough to complete the desired gap. The CD2431
readjusts data alignment in its internal FIFO as needed to maintain alignment with the external
buffer.
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