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參數(shù)資料
| 型號： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁數(shù)： | 163/186頁 |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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CD2431 — Advanced Multi-Protocol Communications Controller
78
Datasheet
For example, if the CD2431 is designed to be DCE and automatic out-of-band flow control is
desired, connect the DTR pin to the remote CTS input. If the CD2431 is to be used as the DTE
side, then the CD2431 CTS output would be connected to the remote CTS input.
Note that if automatic out-of-band flow control is implemented, the activity of the DTR and DSR
pins do not implement the function assigned to those signal names by the signaling conventions of
the CCITT and other standards organization. These names would only apply to these pins if they
are under program control and not under automatic CD2431 control. In fact, the DTR function
enables the modem to go on- and off-line, depending on the state of the pin. If automatic control is
used, then DTR goes inactive when the receive FIFO reached the programmed threshold, thus
causing the modem to drop the connection (carrier) to the remote; this would not be the correct
function based on the state of the receive FIFO.
6.5.3
Line Break Detection and Generation
A line break on the receiver occurs when the input at the RXD (receive data) pin is all zeros (low)
for at least one full character time. This is indicated when the Break bit (RISRL[0]) is set to ‘1’.
Line break generation out of the transmitter is possible when the ETC bit (COR2[5]) is set to ‘1’. A
line break is generated when the output at the TXD pin is all zeroes (low) for at least one full
character time.
Line breaks can be transmitted by embedding certain sequences in the data stream as defined later.
These sequences are valid for transmitting breaks only if ETC is set to ‘1’. The embedded
sequences to transmit a break are listed in Table 12 on page 78.
The ETC mechanism works in ASYNC mode only, though breaks can be detected in ASYNC, PPP,
SLIP, and MNP 4 modes.
Note:
In addition to insert delay, a ‘break’ can also be increased beyond one full character by transmitting
more than one ‘send BREAK’ sequence at a time.
6.5.4
Special Character Transmission
Selected special characters can be sent preemptively by setting the SndSpc bit (STCR[3]). The
CD2431 channel acknowledges the command by clearing the STCR. Along with the SndSpc bit,
the host needs to set-up the three Special Character Select bits (STCR[2:0] to select which
character is to be sent.
Table 12. BREAK Sequencing
Index
Description
00h–81h
Send BREAK – Send a line break for at least one character time.
00h–82h-xxh
Insert delay – To increase the break generation beyond one character time, the insert delay sequence
can be used. The inserted delay is xx, where xx is a binary number. The delay is xx times the ‘tick’ set by
the TPR (Timer Period register). The minimum period of TPR should be 1 millisecond. If the insert delay
sequence is not preceded by a send BREAK sequence, there is an inserted delay of all ‘1’s (high) on the
output for duration xx.
00h–83h
Stop BREAK – This must follow the send BREAK sequence, or the insert delay sequence.
00h–00h
Send NUL – If the user needs to send a NUL character and ETC = 1, the user can embed 00h–00h to
send one NUL character. If there are less than 8-bits per character, the user can also send a NUL
character by ‘sending’ an 80h.
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