
II CORE BLOCK: CPU AND OPERATING MODE
B-II-2-4
EPSON
S1C33L01 FUNCTION PART
Trap Table
Table 2.1 shows the trap table in the C33 Core. Refer to the "S1C33000 Core CPU Manual" for details of exceptions
and Section II-5 in this manual, "ITC (Interrupt Controller)", for interrupts.
Table 2.1
Trap Table
HEX
No.
Vector number
(Hex address)
Exception/interrupt name
Exception/interrupt factor
IDMA
Ch.
Priority
0
0(Base)
Reset
Low input to the reset pin
–
High
1–3
reserved
––
↑
44(Base+10)
Zero divisionDivision instruction–
5
reserved
––
6
6(Base+18)
Address error exceptionMemory access instruction–
7
0x0 or 0x60000 Debugging exception
brk instruction, etc.–
8
8(Base+1C)
NMI
Low input to the NMI pin
–
9–11
reserved
––
C
12(Base+30)
Software exception 0
int instruction–
D13(Base+34)
Software exception 1
int instruction–
E14(Base+38)
Software exception 2
int instruction–
F15(Base+3C)
Software exception 3
int instruction–
10
16(Base+40)
Port input interrupt 0
Edge (rising or falling) or level (High or Low)
1
11
17(Base+44)
Port input interrupt 1Edge (rising or falling) or level (High or Low)
2
12
18(Base+48)
Port input interrupt 2Edge (rising or falling) or level (High or Low)
3
13
19(Base+4C)
Port input interrupt 3
Edge (rising or falling) or level (High or Low)
4
14
20(Base+50)
Key input interrupt 0
Rising or falling edge
–
15
21(Base+54)
Key input interrupt 1Rising or falling edge
–
16
22(Base+58)
High-speed DMA Ch.0
High-speed DMA Ch.0, end of transfer
5
17
23(Base+5C)
High-speed DMA Ch.1
High-speed DMA Ch.1, end of transfer
6
18
24(Base+60)
High-speed DMA Ch.2
High-speed DMA Ch.2, end of transfer–
19
25(Base+64)
High-speed DMA Ch.3
High-speed DMA Ch.3, end of transfer–
1A
26(Base+68)
IDMA
Intelligent DMA, end of transfer–
27–29
reserved
––
1E
30(Base+78)
16-bit programmable timer 0
Timer 0 comparison B
7
1F
31(Base+7C)
Timer 0 comparison A
8
32–33
reserved
––
22
34(Base+88)
16-bit programmable timer 1
Timer 1 comparison B
9
23
35(Base+8C)
Timer 1 comparison A
10
36–37reserved
––
26
38(Base+98)
16-bit programmable timer 2
Timer 2 comparison B
11
27
39(Base+9C)
Timer 2 comparison A
12
40–41
reserved
––
2A
42(Base+A8)
16-bit programmable timer 3
Timer 3 comparison B
13
2B
43(Base+AC)
Timer 3 comparison A
14
44–45
reserved
––
2E
46(Base+B8)
16-bit programmable timer 4
Timer 4 comparison B
15
2F
47(Base+BC)
Timer 4 comparison A
16
48–49
reserved
––
32
50(Base+C8)
16-bit programmable timer 5
Timer 5 comparison B
17
33
51(Base+CC)
Timer 5 comparison A
18
34
52(Base+D0)
8-bit programmable timerTimer 0 underflow19
35
53(Base+D4)
Timer 1 underflow20
36
54(Base+D8)
Timer 2 underflow21
37
55(Base+DC)
Timer 3 underflow22
38
56(Base+E0)
Serial interface Ch.0
Receive error–
39
57(Base+E4)
Receive buffer full
23
3A
58(Base+E8)
Transmit buffer empty
24
59
reserved
––
3C
60(Base+F0)
Serial interface Ch.1
Receive error–
3D
61(Base+F4)
Receive buffer full
25
3E
62(Base+F8)
Transmit buffer empty
26
63
reserved
––
40
64(Base+100)
A/D converterA/D converter, end of conversion27
41
65(Base+104)
Clock timer
Falling edge of 32 Hz, 8 Hz, 2 Hz or 1 Hz signal
1-minuet, 1-hour or specified time count up
–
66–67reserved
––
44
68(Base+110)
Port input interrupt 4Edge (rising or falling) or level (High or Low)
28
45
69(Base+114)
Port input interrupt 5
Edge (rising or falling) or level (High or Low)
29
46
70(Base+118)
Port input interrupt 6
Edge (rising or falling) or level (High or Low)
30
↓
47
71(Base+11C)
Port input interrupt 7Edge (rising or falling) or level (High or Low)
31Low
Base = Set value in the TTBR register (0x48134 to 0x48137); 0xC00000 by default.