
1
OUTLINE
A-6
EPSON
S1C33L01 PRODUCT PART
Pin name
Pin No.
I/O
Pull-up
Function
#CE3
57
O
–
Area 3 chip enable
#RD
51
O
–
Read signal
#EMEMRD
50
O
–
Read signal for internal ROM emulation memory
#WRL
#WR
#WE
52
O
–
#WRL: Write (low byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#WR:
Write signal when SBUSST(D3/0x4812E) = "1"
#WE:
DRAM write signal (default)
#WRH
#BSH
53
O
–
#WRH: Write (high byte) signal when SBUSST(D3/0x4812E) = "0" (default)
#BSH: Bus strobe (high byte) signal when SBUSST(D3/0x4812E) = "1"
#HCAS
76
O
–
#HCAS:
DRAM column address strobe (high byte) signal
#LCAS
75
O
–
#LCAS:
DRAM column address strobe (low byte) signal
BCLK
49
O
–
Bus clock output
P34
#BUSREQ
#CE6
120
I/O
–
P34:
I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ: Bus release request input when CFP34(D4/0x402DC) = "1"
#CE6:
Area 6 chip enable when CFP34(D4/0x402DC) = "1"
and IOC34(D4/0x402DE) = "1"
P35
#BUSACK
119
I/O
–
P35:
I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK: Bus acknowledge output when CFP35(D5/0x402DC) = "1"
P30
#WAIT
#CE4&5
124
I/O
–
P30:
I/O port when CFP30(D0/0x402DC) = "0" (default)
#WAIT:
Wait cycle request input when CFP30(D0/0x402DC) = "1"
#CE4&5:
Areas 4&5 chip enable when CFP30(D0/0x402DC) = "1"
and IOC30(D0/0x402DE) = "1"
P20
#DRD
134
I/O
–
P20:
I/O port when CFP20(D0/0x402D8) = "0" (default)
#DRD:
DRAM read signal output for successive RAS mode
when CFP20(D0/0x402D8) = "1"
P21
#DWE
#GAAS
133
I/O
P21:
I/O port when CFP21(D1/0x402D8) = "0" and CFEX2(D2/0x402DF) = "0"
(default)
#DWE:
DRAM write signal output for successive RAS mode
when CFP21(D1/0x402D8) = "1" and CFEX2(D2/0x402DF) = "0"
#GAAS:
Area address strobe output for GA when CFEX2(D2/0x402DF) = "1"
P31
#BUSGET
#GARD
123
I/O
P31:
I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0"
(default)
#BUSGET: Bus status monitor signal output for bus request
when CFP31(D1/0x402DC) = "1" and CFEX3(D3/0x402DF) = "0"
#GARD:
Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
EA10MD1
166
I
With
pull-up
Area 10 boot mode selection
EA10MD1
EA10MD0
Mode
1
External ROM mode
EA10MD0
167
I
–
1
0
Internal ROM mode
0
1
OTP mode
0
Internal ROM emulation
Table 1.3.3
List of Pins for HSDMA Control Signals
Pin name
Pin No.
I/O
Pull-up
Function
K50
#DMAREQ0
74
I
With
pull-up
K50:
Input port when CFK50(D0/0x402C0) = "0" (default)
#DMAREQ0: HSDMA Ch. 0 request input when CFK50(D0/0x402C0) = "1"
K51
#DMAREQ1
73
I
With
pull-up
K51:
Input port when CFK51(D1/0x402C0) = "0" (default)
#DMAREQ1: HSDMA Ch. 1 request input when CFK51(D1/0x402C0) = "1"
K53
#DMAREQ2
70
I
With
pull-up
K53:
Input port when CFK53(D3/0x402C0) = "0" (default)
#DMAREQ2: HSDMA Ch. 2 request input when CFK53(D3/0x402C0) = "1"
K54
#DMAREQ3
69
I
With
pull-up
K54:
Input port when CFK54(D4/0x402C0) = "0" (default)
#DMAREQ3: HSDMA Ch. 3 request input when CFK54(D4/0x402C0) = "1"
P32
#DMAACK0
122
I/O
–
P32:
I/O port when CFP32(D2/0x402DC) = "0" (default)
#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1"
P33
#DMAACK1
121
I/O
–
P33:
I/O port when CFP33(D3/0x402DC) = "0" (default)
#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1"