
4
PERIPHERAL CIRCUITS
A-58
EPSON
S1C33L01 PRODUCT PART
Name
Address
Register name
Bit
Setting
Init.
R/W
Remarks
D7–6
D5
D4
D3
D2
D1
D0
n/a
FPFRAME Start Position Bit 5
FPFRAME Start Position Bit 4
FPFRAME Start Position Bit 3
FPFRAME Start Position Bit 2
FPFRAME Start Position Bit 1
FPFRAME Start Position Bit 0
0
R/W
039FFE9
(B)
SID13705
REG[09h]
FPFRAME start
position
FPFRAME start position (lines)
= REG[09h]
–
D7
D6
D5
D4
D3
D2
D1
D0
Vertical Non-Display Status
n/a
Vertical Non-Display Period Bit 5
Vertical Non-Display Period Bit 4
Vertical Non-Display Period Bit 3
Vertical Non-Display Period Bit 2
Vertical Non-Display Period Bit 1
Vertical Non-Display Period Bit 0
0
R
R/W
039FFEA
(B)
SID13705
REG[0Ah]
Vertical
non-display
period
Vertical non-display period
(lines) = REG[0Ah] bits [5:0]
–
1 Non-display 0 Display
D7–6
D5
D4
D3
D2
D1
D0
n/a
MOD Rate Bit 5
MOD Rate Bit 4
MOD Rate Bit 3
MOD Rate Bit 2
MOD Rate Bit 1
MOD Rate Bit 0
0
R/W
039FFEB
(B)
SID13705
REG[0Bh]
MOD rate
register
–
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 Start Address Bit 7
Screen 1 Start Address Bit 6
Screen 1 Start Address Bit 5
Screen 1 Start Address Bit 4
Screen 1 Start Address Bit 3
Screen 1 Start Address Bit 2
Screen 1 Start Address Bit 1
Screen 1 Start Address Bit 0
0
R/W
039FFEC
(B)
SID13705
REG[0Ch]
Screen 1 start
address
register (LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Screen 1 Start Address Bit 15
Screen 1 Start Address Bit 14
Screen 1 Start Address Bit 13
Screen 1 Start Address Bit 12
Screen 1 Start Address Bit 11
Screen 1 Start Address Bit 10
Screen 1 Start Address Bit 9
Screen 1 Start Address Bit 8
0
R/W
039FFED
(B)
SID13705
REG[0Dh]
Screen 1 start
address
register (MSB)
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 Start Address Bit 7
Screen 2 Start Address Bit 6
Screen 2 Start Address Bit 5
Screen 2 Start Address Bit 4
Screen 2 Start Address Bit 3
Screen 2 Start Address Bit 2
Screen 2 Start Address Bit 1
Screen 2 Start Address Bit 0
0
R/W
039FFEE
(B)
SID13705
REG[0Eh]
Screen 2 start
address
register (LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Screen 2 Start Address Bit 15
Screen 2 Start Address Bit 14
Screen 2 Start Address Bit 13
Screen 2 Start Address Bit 12
Screen 2 Start Address Bit 11
Screen 2 Start Address Bit 10
Screen 2 Start Address Bit 9
Screen 2 Start Address Bit 8
0
R/W
039FFEF
(B)
SID13705
REG[0Fh]
Screen 2 start
address
register (MSB)
D7–1
D0
n/a
Screen 1 Start Address Bit 16
(for Portrait mode only)
0
R/W
039FFF0
(B)
SID13705
REG[10h]
Screen 1
start address
overflow register
–
D7
D6
D5
D4
D3
D2
D1
D0
Memory Address Offset Bit 7
Memory Address Offset Bit 6
Memory Address Offset Bit 5
Memory Address Offset Bit 4
Memory Address Offset Bit 3
Memory Address Offset Bit 2
Memory Address Offset Bit 1
Memory Address Offset Bit 0
0
R/W
039FFF1
(B)
SID13705
REG[11h]
Memory
address offset
register