
4
PERIPHERAL CIRCUITS
S1C33L01 PRODUCT PART
EPSON
A-57
Name
Address
Register name
Bit
Setting
Init.
R/W
Remarks
SID13705 = "001001"
Revision = "01"
D7
D6
D5
D4
D3
D2
D1
D0
Product Code Bit 5
Product Code Bit 4
Product Code Bit 3
Product Code Bit 2
Product Code Bit 1
Product Code Bit 0
Revision Code Bit 1
Revision Code Bit 0
0
1
0
1
0
1
R
039FFE0
(B)
SID13705
REG[00h]
Revision code
register
See SID13705 Hardware
Functional Specification
D7
D6
D5
D4
D3
D2
D1
D0
TFT/STN
Dual/Single
Color/Mono
FP Line Polarity
FP Flame Polarity
Mask FPSHIFT
Data Width Bit 1
Data Width Bit 0
0
R/W
039FFE1
(B)
SID13705
REG[01h]
Mode register 0
1 TFT/D-TFD 0 STN
1 Dual
0 Single
1 Color
0 Mono
1 Active high
0 Active low
1 Active high
0 Active low
1 Masked
0 Not masked
D7
D6
D5
D4
D3
D2
D1
D0
Bit-Per-Pixel Bit 1
Bit-Per-Pixel Bit 0
High Performance
Input Clock Divide (Clk / 2)
Display Blank
Frame Repeat
Hardware Video Invert Enable
Software Video Invert
0
R/W
039FFE2
(B)
SID13705
REG[02h]
Mode register 1
1 MClk=PClk 0 MClk=PClk/x
1 Clk/1
0 Clk/2
1 Displayed
0 Blanked
1 Repeated
0 Not repeated
1 Inverted
0 GPIO4
1 Inverted
0 Normal
1
0
1
0
1
0
Bit[1:0]
Bit-Per-Pixel
8 bpp
4 bpp
2 bpp
1 bpp
D7–4
D3
D2
D1
D0
n/a
LCDPWR Override
Hardware Power Save Enable
Software Power Save Bit 1
Software Power Save Bit 0
0
R/W
039FFE3
(B)
SID13705
REG[03h]
Mode register 2
1 Inactive
0 Controlled
1 Enabled
0 GPIO0
1
0
1
0
1
0
Bit[1:0]
Mode
Normal operation
reserved
Power save mode
–
D7
D6
D5
D4
D3
D2
D1
D0
n/a
Horizontal Panel Size Bit 6
Horizontal Panel Size Bit 5
Horizontal Panel Size Bit 4
Horizontal Panel Size Bit 3
Horizontal Panel Size Bit 2
Horizontal Panel Size Bit 1
Horizontal Panel Size Bit 0
0
R/W
039FFE4
(B)
SID13705
REG[04h]
Horizontal
panel size
register
–
Value =
(Horizontal panel resolution/8)
- 1
D7
D6
D5
D4
D3
D2
D1
D0
Vertical Panel Size Bit 7
Vertical Panel Size Bit 6
Vertical Panel Size Bit 5
Vertical Panel Size Bit 4
Vertical Panel Size Bit 3
Vertical Panel Size Bit 2
Vertical Panel Size Bit 1
Vertical Panel Size Bit 0
0
R/W
039FFE5
(B)
SID13705
REG[05h]
Vertical panel
size register
(LSB)
Value =
Vertical panel resolution - 1
D7–2
D1
D0
n/a
Vertical Panel Size Bit 9
Vertical Panel Size Bit 8
0
R/W
039FFE6
(B)
SID13705
REG[06h]
Vertical panel
size register
(MSB)
Value =
Vertical panel resolution - 1
D7–5
D4
D3
D2
D1
D0
n/a
FPLINE Start Position Bit 4
FPLINE Start Position Bit 3
FPLINE Start Position Bit 2
FPLINE Start Position Bit 1
FPLINE Start Position Bit 0
0
R/W
039FFE7
(B)
SID13705
REG[07h]
FPLINE start
position
FPLINE start position (pixels)
= (REG[07h] + 2) x 8
–
D7–5
D4
D3
D2
D1
D0
n/a
Horizontal Non-Display Period Bit 4
Horizontal Non-Display Period Bit 3
Horizontal Non-Display Period Bit 2
Horizontal Non-Display Period Bit 1
Horizontal Non-Display Period Bit 0
0
R/W
039FFE8
(B)
SID13705
REG[08h]
Horizontal
non-display
period
Horizontal non-display period
(pixels) = (REG[08h] + 4) x 8
–