
III PERIPHERAL BLOCK: 8-BIT PROGRAMMABLE TIMERS
S1C33L01 FUNCTION PART
EPSON
B-III-3-13
CFEX1: P10, P11, P13 port extended function (D1) / Port function extension register (0x402DF)
CFEX0: P12, P14 port extended function (D0) / Port function extension register (0x402DF)
Sets whether the function of an I/O-port pin is to be extended.
Write "1": Function-extended pin
Write "0": I/O-port/peripheral-circuit pin
Read: Valid
When CFEX[1:0] is set to "1", the P13–P10 ports function as debug signal output ports. When CFEX[1:0] = "0", the
CFP1[3:0] bit becomes effective, so the settings of these bits determine whether the P13–P10 ports function as I/O
port s or timer underflow signal output ports.
At cold start, CFEX[1:0] is set to "1" (function-extended pins). At hot start, CFEX[1:0] retains its state from prior to
the initial reset.
RLD07–RLD00: Timer 0 reload data (D[7:0]) / 8-bit timer 0 reload data register (0x40161)
RLD17–RLD10: Timer 1 reload data (D[7:0]) / 8-bit timer 1 reload data register (0x40165)
RLD27–RLD20: Timer 2 reload data (D[7:0]) / 8-bit timer 2 reload data register (0x40169)
RLD37–RLD30: Timer 3 reload data (D[7:0]) / 8-bit timer 3 reload data register (0x4016D)
Set the initial counter value of each timer.
The reload data set in this register is loaded into each counter, and the counter starts counting down beginning with
this data, which is used as the initial count.
There are two cases in which the reload data is loaded into the counter: when data is preset after "1" is written to
PSETx, or when data is automatically reloaded upon counter underflow.
At initial reset, RLD is not initialized.
PTD07–PTD00: Timer 0 counter data (D[7:0]) / 8-bit timer 0 counter data (0x40162)
PTD17–PTD10: Timer 1 counter data (D[7:0]) / 8-bit timer 1 counter data (0x40166)
PTD27–PTD20: Timer 2 counter data (D[7:0]) / 8-bit timer 2 counter data (0x4016A)
PTD37–PTD30: Timer 3 counter data (D[7:0]) / 8-bit timer 3 counter data (0x4016E)
The 8-bit programmable timer data can be read out from these bits.
These bits function as buffers that retain the counter data when read out, enabling the data to be read out at any time.
At initial reset, PTD is not initialized.
PSET0: Timer 0 preset (D1) / 8-bit timer 0 control register (0x40160)
PSET1: Timer 1 preset (D1) / 8-bit timer 1 control register (0x40164)
PSET2: Timer 2 preset (D1) / 8-bit timer 2 control register (0x40168)
PSET3: Timer 3 preset (D1) / 8-bit timer 3 control register (0x4016C)
Preset the reload data in the counter.
Write "1": Preset
Write "0": Invalid
Read: Always "0"
The reload data of RLDx is preset in the counter of timer x by writing "1" to PSETx. If the counter is preset when in
a RUN state, the counter starts counting immediately after the reload data is preset.
If the counter is preset when in a STOP state, the reload data that has been preset is retained.
Writing "0" results in No Operation.
Since PSETx is a write-only bit, its content when read is always "0".