
II CORE BLOCK: ITC (Interrupt Controller)
S1C33L01 FUNCTION PART
EPSON
B-II-5-21
Programming Notes
(1) In cases when an interrupt factor that is used for restarting from the standby mode has been set to invoke IDMA,
IDMA is started up by the interrupt at its occurrence. In SLEEP mode, the high-speed (OSC3) oscillation
circuit also starts operating. However, if an interrupt to be generated upon completion of IDMA is disabled at
the setting of IDMA side, no interrupt request is signaled to the CPU. Therefore, the CPU remains idle until the
next interrupt request is generated.
(2) As the S1C33000 Core CPU function, the IL allows interrupt levels to be set in the range of 0 to 15. However,
since the interrupt priority register in the C33 Core Block consists of three bits, interrupt levels in each
interrupt system can only be set for up to 8.
(3) When the reset-only method is used to reset the interrupt factor flag (by writing "1"), if a read-modify-write
instruction (e.g., bset, bclr, or bnot) is executed, the other interrupt factor flags at the same address that have
been set to "1" are reset by a write. This requires caution. In cases when the read/write method is used to reset
the interrupt factor flag (by writing "0"), all factor flags for which "0" has been written are reset. When a
read-modify-write operation is performed, an interrupt factor may occur between reads and writes, so be
careful when using this method.
The same applies to the set-only method and read/write method for the IDMA request and IDMA enable
registers.
(4) After an initial reset, the interrupt factor flags and interrupt priority registers all become indeterminate. To
prevent unwanted interrupts or IDMA requests from being generated inadvertently, be sure to reset these flags
and registers in the software application.
(5) To prevent another interrupt from being generated for the same factor again after generation of an interrupt,be
sure to reset the interrupt factor flag before enabling interrupts and setting the PSR again or executing the reti
instruction.