
7 HARDWARE ROTATION
SID13705 PROGRAMMING NOTES
EPSON
C-2-27
AND EXAMPLES
7.4 Registers
This section describes the registers used to set portrait mode operation.
The Screen 1 Start Address registers must be set correctly for portrait mode. In portrait mode the
Start Address registers form a byte offset, as opposed to a word offset, into display memory.
The initial required offset is the portrait mode stride (in bytes) less one.
The line byte count register informs the SID13705 block of the stride, in bytes, between two
consecutive lines of display in portrait mode. The Line Byte Count register only affects portrait
mode operation and are ignored when the SID13705 block is in landscape display mode.
The portrait mode register contains several items for portrait mode support.
The first is the Portrait Mode Enable bit. When this bit is “0” the SID13705 block is in landscape
mode and the remainder of the settings in this register as well as the Line Byte Count in REG[1Ch]
are ignored. Set this bit to “1” to enable portrait mode.
The portrait mode select bit selects between the “Default Mode” and the “Alternate Mode”.
Setting this bit to “0” selects the default portrait mode while setting this bit to “1” enables the
alternate portrait mode.
Portrait Mode Memory Clock Select is another power saving measure which can be enabled if the
final MCLK value is less than or equal to 25 MHz. Memory Clock Select results in the SID13705
block temporarily increasing the memory clock circuitry on CPU access and resuming the slower
speed when the access is complete. This results in better performance while using the least power.
In portrait display mode the CLKI (input clock) is routed to the portrait section of the SID13705
block as CLK. From the CLK signal the MCLK value can be determined from table 8-8 of the
Hardware Functional Specification, document number X27A-A-001-xx. If MCLK is determined
to be less than or equal to 25 MHz then Portrait Mode Memory Clock Select may be enabled.
REG[0Ch] Screen 1 Start Word Address LSB
bit 7bit 6bit 5bit 4
bit 3bit 2bit 1bit 0
REG[0Dh] Screen 1 Start Word Address MSB
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
REG[0Eh] Screen 1 Start Word Address MSB
n/an/a
n/a
bit 16
REG[1Ch] Line Byte Count Register
bit 7bit 6bit 5bit 4
bit 3bit 2bit 1bit 0
REG[1Bh] Portrait Mode Register
Portrait Mode
Enable
Portrait Mode
Select
n/a
Portrait Mode
Memory Clock
Select
Portrait Mode
Pixel Clock
Select Bit 1
Portrait Mode
Pixel Clock
Select Bit 0