
1
OUTLINE
A-8
EPSON
S1C33L01 PRODUCT PART
Pin name
Pin No.
I/O
Pull-up
Function
P04
SIN1
#DMAACK2
147
I/O
–
P04:
I/O port when CFP04(D4/0x402D0) = "0" and CFEX4(D4/0x402DF) = "0"
(default)
SIN1:
Serial I/F Ch. 1 data input when CFP04(D4/0x402D0) = "1"
and CFEX4(D4/0x402DF) = "0"
#DMAACK2: HSDMA Ch. 2 acknowledge output when CFEX4(D4/0x402DF) = "1"
P05
SOUT1
#DMAEND2
146
I/O
–
P05:
I/O port when CFP05(D5/0x402D0) = "0" and CFEX5(D5/0x402DF) = "0"
(default)
SOUT1:
Serial I/F Ch. 1 data output when CFP05(D5/0x402D0) = "1"
and CFEX5(D5/0x402DF) = "0"
#DMAEND2: HSDMA Ch. 2 end-of-transfer signal outputwhen CFEX5(D5/0x402DF)= "1"
P06
#SCLK1
#DMAACK3
145
I/O
–
P06:
I/O port when CFP06(D6/0x402D0) = "0" and CFEX6(D6/0x402DF) = "0"
(default)
#SCLK1:
Serial I/F Ch. 1 clock input/output when CFP06(D6/0x402D0) = "1"
and CFEX6(D6/0x402DF) = "0"
#DMAACK3: HSDMA Ch. 3 acknowledge output when CFEX6(D6/0x402DF) = "1"
P07
#SRDY1
#DMAEND3
144
I/O
–
P07:
I/O port when CFP07(D7/0x402D0) = "0" and CFEX7(D7/0x402DF) = "0"
(default)
#SRDY1:
Serial I/F Ch. 1 ready signal output when CFP07(D7/0x402D0) = "1"
and CFEX5(D5/0x402DF) = "0"
#DMAEND3: HSDMA Ch. 3 end-of-transfer signal outputwhen CFEX7(D7/0x402DF)= "1"
P10
EXCL0
T8UF0
DST0
142
I/O
–
P10:
I/O port when CFP10(D0/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL0:
16-bit timer 0 event counter input when CFP10(D0/0x402D4) = "1",
IOC10(D0/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF0:
8-bit timer 0 output when CFP10(D0/0x402D4) = "1",
IOC10(D0/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"
DST0:
DST0 signal output when CFEX1(D1/0x402DF) = "1" (default)
P11
EXCL1
T8UF1
DST1
141
I/O
–
P11:
I/O port when CFP11(D1/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL1:
16-bit timer 1 event counter input when CFP11(D1/0x402D4) = "1",
IOC11(D1/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF1:
8-bit timer 1 output when CFP11(D1/0x402D4) = "1",
IOC11(D1/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"
DST1:
DST1 signal output when CFEX1(D1/0x402DF) = "1" (default)
P12
EXCL2
T8UF2
DST2
140
I/O
–
P12:
I/O port when CFP12(D2/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
EXCL2:
16-bit timer 2 event counter input when CFP12(D2/0x402D4) = "1",
IOC12(D2/0x402D6) = "0" and CFEX0(D0/0x402DF) = "0"
T8UF2:
8-bit timer 2 output when CFP12(D2/0x402D4) = "1",
IOC12(D2/0x402D6) = "1" and CFEX0(D0/0x402DF) = "0"
DST2:
DST2 signal output when CFEX0(D0/0x402DF) = "1" (default)
P13
EXCL3
T8UF3
DPCO
139
I/O
–
P13:
I/O port when CFP13(D3/0x402D4) = "0" and CFEX1(D1/0x402DF) = "0"
EXCL3:
16-bit timer 3 event counter input when CFP13(D3/0x402D4) = "1",
IOC13(D3/0x402D6) = "0" and CFEX1(D1/0x402DF) = "0"
T8UF3:
8-bit timer 3 output when CFP13(D3/0x402D4) = "1",
IOC13(D3/0x402D6) = "1" and CFEX1(D1/0x402DF) = "0"
DPCO:
DPCO signal output when CFEX1(D1/0x402DF) = "1" (default)
P14
FOSC1
DCLK
138
I/O
–
P14:
I/O port when CFP14(D4/0x402D4) = "0" and CFEX0(D0/0x402DF) = "0"
FOSC1:
OSC1 clock output when CFP14(D4/0x402D4) = "1"
and CFEX0(D0/0x402DF) = "0"
DCLK:
DCLK signal output when CFEX0(D0/0x402DF) = "1" (default)
P15
EXCL4
#DMAEND0
136
I/O
–
P15:
I/O port when CFP15(D5/0x402D4) = "0" (default)
EXCL4:
16-bit timer 4 event counter input when CFP15(D5/0x402D4) = "1"
and IOC15(D5/0x402D6) = "0"
#DMAEND0: HSDMA Ch. 0 end-of-transfer signal outputwhen CFP15(D5/0x402D4) = "1"
and IOC15(D5/0x402D6) = "1"
P16
EXCL5
#DMAEND1
135
I/O
–
P16:
I/O port when CFP16(D6/0x402D4) = "0" (default)
EXCL5:
16-bit timer 5 event counter input when CFP16(D6/0x402D4) = "1"
and IOC16(D6/0x402D6) = "0"
#DMAEND1: HSDMA Ch. 1 end-of-transfer signal outputwhen CFP16(D6/0x402D4) = "1"
and IOC16(D6/0x402D6) = "1"