
1
OUTLINE
S1C33L01 PRODUCT PART
EPSON
A-9
Pin name
Pin No.
I/O
Pull-up
Function
P22
TM0
132
I/O
–
P22:
I/O port when CFP22(D2/0x402D8) = "0" (default)
TM0:
16-bit timer 0 output when CFP22(D2/0x402D8) = "1"
P23
TM1
130
I/O
–
P23:
I/O port when CFP23(D3/0x402D8) = "0" (default)
TM1:
16-bit timer 1 output when CFP23(D3/0x402D8) = "1"
P24
TM2
129
I/O
–
P24:
I/O port when CFP24(D4/0x402D8) = "0" (default)
TM2:
16-bit timer 2 output when CFP24(D4/0x402D8) = "1"
P25
TM3
128
I/O
–
P25:
I/O port when CFP25(D5/0x402D8) = "0" (default)
TM3:
16-bit timer 3 output when CFP25(D5/0x402D8) = "1"
P26
TM4
127
I/O
–
P26:
I/O port when CFP26(D6/0x402D8) = "0" (default)
TM4:
16-bit timer 4 output when CFP26(D6/0x402D8) = "1"
P27
TM5
126
I/O
–
P27:
I/O port when CFP27(D7/0x402D8) = "0" (default)
TM5:
16-bit timer 5 output when CFP27(D7/0x402D8) = "1"
Table 1.3.5
List of Pins for LCD Controller (SID13705)
Pin name
Pin No.
I/O
Pull-up
Function
FPDAT11
GPIO4
INVERSE
92
I/O
–
FPDAT11: Panel data bit 11 for TFT/MD-TFD panels
GPIO4:
General-purpose I/O pin (default)
INVERSE: Inverse video select pin
FPDAT10
GPIO3
93
I/O
–
FPDAT10: Panel data bit 10 for TFT/MD-TFD panels
GPIO3:
General-purpose I/O pin (default)
FPDAT9
GPIO2
94
I/O
–
FPDAT9:
Panel data bit 9 for TFT/MD-TFD panels
GPIO2:
General-purpose I/O pin (default)
FPDAT8
GPIO1
96
I/O
–
FPDAT8:
Panel data bit 8 for TFT/MD-TFD panels
GPIO1:
General-purpose I/O pin (default)
FPDAT[7:0]
98–100,
102–105,
107
O
–
Panel data bits [7:0]
FPFRAME
109
O
–
Frame pulse
FPLINE
108
O
–
Line pulse
FPSHIFT
97
O
–
Shift clock
LCDPWR
112
O
–
Active high LCD power control
DRDY
MOD
FPSHIFT2
110
O
–
DRDY:
TFT/MD-TFD display enable
MOD:
LCD backplane bias (default)
FPSHIFT2: Second shift clock for color passive panel (8-bit single format 1)
CLKI
161
I
–
External clock input
CKSEL[2:0]
157–159
I
–
Clock source selection
CKSEL2
CKSEL1
CKSEL0
Clock source
1
reserved
1
0
13705 disable mode
1
0
1
External input clock from the CLKI pin
1
0
OSC3 oscillation clock x 1/4
0
1
OSC3 oscillation clock x 1/3
0
1
0
OSC3 oscillation clock x 1/2
0
1
OSC3 oscillation clock
0
PLL output clock
CNF3
156
I
–
Access method (endian) selection
1: Big endian, 0: Little endian
GPIO0
91
I/O
–
General-purpose I/O pin
1 The SID13705 CNF[2:0] pins are not available in the S1C33L01 and have been replaced with the CKSEL[2:0]
pins. Refer to "SID13705 Hardware Functional Specification" for details of the LCD interface pins.
2 Note that some pins in Table 1.3.5 use different I/O interface level (power source) from other LCD controller
pins.
CLKI, CKSEL[2:0], CNF3 pins (signals): VDDE1 (power voltage for I/O interface)
Other pins (signals):
VDDE2 (power voltage for LCD interface)