
1
OUTLINE
A-2
EPSON
S1C33L01 PRODUCT PART
Interrupt controller:
Possible to invoke DMA
Input interrupt
10 types (programmable)
DMA controller interrupt
5 types
16-bit programmable timer interrupt 12 types
8-bit programmable timer interrupt
4 types
Serial interface interrupt
6 types
A/D converter interrupt
1 type
Clock timer interrupt
1 type
General-purpose input
Shared with the I/O pins for internal peripheral circuits
and output ports:
Input port
13 bits
I/O port
29 bits
External bus interface
BCU (bus control unit) built-in
24-bit address bus (internal 28-bit processing)
16-bit data bus
Data size is selectable from 8 bits and 16 bits in each area.
Little-endian memory access; big-endian may be set in each area.
Memory mapped I/O
Chip enable and wait control circuits built-in
DRAM direct interface function built-in
Supports fast page mode and EDO page mode.
Supports self-refresh and CAS-before RAS refresh.
Supports burst ROM.
Operating conditions and power consumption
Operating voltage:
Core (VDD)
1.8 V to 3.6 V
I/O (VDDE1)
1.8 V to 5.5 V
LCD I/F (VDDE2)
1.8 V to 5.5 V
Operating clock frequency: CPU
50 MHz max. (when core voltage = 3.3 V
±0.3 V)
40 MHz max. (when core voltage = 3.0 V
±0.3 V)
LCD controller
25 MHz max. (when core voltage = 3.3 V
±0.3 V)
Operating temperature:
-40 to 85
°C
Power consumption:
During SLEEP
4
W typ.
During HALT
130 mW typ.
(3.3 V, 50 MHz, LCD controller enabled)
100 mW typ.
(3.3 V, 50 MHz, LCD controller is in power-save mode)
During execution
230 mW typ.
(3.3 V, 50 MHz, LCD controller enabled)
Note: The values of power consumption during execution were measured when a test
program that consisted of 55% load instructions, 23% arithmetic operation
instructions, 1% mac instruction, 12% branch instructions and 9% ext
instruction was being continuously executed.
The LCD controller is configured with 640
× 480 display resolution, 1 bpp mode
and a 25 MHz operating clock.
Supply form
QFP18-176pin plastic package