
I OUTLINE: LIST OF PINS
S1C33L01 FUNCTION PART
EPSON
B-I-3-5
Pin name
I/O
Pull-up
Function
P25
TM3
I/O
–
P25:
I/O port when CFP25(D5/0x402D8) = "0" (default)
TM3:
16-bit timer 3 output when CFP25(D5/0x402D8) = "1"
P26
TM4
I/O
–
P26:
I/O port when CFP26(D6/0x402D8) = "0" (default)
TM4:
16-bit timer 4 output when CFP26(D6/0x402D8) = "1"
P27
TM5
I/O
–
P27:
I/O port when CFP27(D7/0x402D8) = "0" (default)
TM5:
16-bit timer 5 output when CFP27(D7/0x402D8) = "1"
P31
#BUSGET
#GARD
I/O
P31:
I/O port when CFP31(D1/0x402DC) = "0" and CFEX3(D3/0x402DF) = "0" (default)
#BUSGET:
Bus status monitor signal output for bus request when CFP31(D1/0x402DC) = "1"
and CFEX3(D3/0x402DF) = "0"
#GARD:
Area read signal output for GA when CFEX3(D3/0x402DF) = "1"
P32
#DMAACK0
I/O
–
P32:
I/O port when CFP32(D2/0x402DC) = "0" (default)
#DMAACK0: HSDMA Ch. 0 acknowledge output when CFP32(D2/0x402DC) = "1"
P33
#DMAACK1
I/O
–
P33:
I/O port when CFP33(D3/0x402DC) = "0" (default)
#DMAACK1: HSDMA Ch. 1 acknowledge output when CFP33(D3/0x402DC) = "1"
P34
#BUSREQ
#CE6
I
–
P34:
I/O port when CFP34(D4/0x402DC) = "0" (default)
#BUSREQ:
Bus release requestinput when CFP34(D4/0x402DC)= "1" and IOC34(D4/0x402DE)= "0"
#CE6:
Area 6 chip enable when CFP34(D4/0x402DC) = "1" and IOC34(D4/0x402DE) = "1"
P35
#BUSACK
I/O
–
P35:
I/O port when CFP35(D5/0x402DC) = "0" (default)
#BUSACK:
Bus acknowledge output when CFP35(D5/0x402DC) = "1"
Table 3.4
List of Pins for Clock Generator and Oscillation Circuits
Pin name
I/O
Pull-up
Function
OSC1
I
–
Low-speed (OSC1) oscillation input (32 kHz crystal oscillator or external clock input)
OSC2
O
–
Low-speed (OSC1) oscillation output
OSC3
I
–
High-speed (OSC3) oscillation input (crystal/ceramic oscillator or external clock input)
OSC4
O
–
High-speed (OSC3) oscillation output
PLLS[1:0]
I
–
PLL set-up pins
PLLS1
PLLS0
fin (fOSC3)
fout (fPSCIN)
1
10–30MHz
20–60MHz
1
10–25MHz
20–50MHz
2
0
1
10–15MHz
40–60MHz
1
10–12.5MHz
40–50MHz
2
0
PLL is not used
L
1: ROM-less model with 3.3 V ± 0.3 V operating voltage
2: ROM built-in model, or 3.0 V ± 0.3 V operating voltage
PLLC
–
Capacitor connecting pin for PLL
Table 3.5
List of Other Pins
Pin name
I/O
Pull-up/down
Function
ICEMD
IWith
pull-down
High-impedance control input pin
When this pin is set to High, all the outputpins go into high-impedance state. This makes itpossible
to disable the S1C33 chip on the board.
DSIO
I/O
With
pull-up
Serial I/O pin for debugging
This pin is used to communicate with the debugging tool S5U1C33000H.
#X2SPD
I
–
Clock doubling mode set-up pin
1: CPU clock = bus clock x 1, 0: CPU clock = bus clock x 2
#NMI
IWith
pull-up
NMI request input pin
#RESET
IWith
pull-up
Initial reset input pin
Note:
"#" in the pin names indicates that the signal is low active.