
5 REGISTERS
C-1-12
EPSON
SID13705 HARDWARE FUNCTIONAL
SPECIFICATION
bit 3
LCDPWR Override
When this bit = 1, LCDPWR is forced inactive, by-passing the LCD power sequencing.
The 127 frame delay between Hardware Power Save and the LCD panel control signals
is reduced to a single line. When this bit = 0, LCDPWR is controlled by the power
sequencing logic within the SID13705 block.
bit 2
Hardware Power Save Enable
When this bit = 1 GPIO0 is used as the Hardware Power Save input pin. When this bit =
0, GPIO0 operates normally.
bits 1-0
Software Power Save Bits [1: 0]
These bits select the Power Save Mode as shown in the following table.
Refer to Section 10 “POWER SAVE MODES” on page C-1-34 for a complete descrip-
tion of the power save modes.
bits 6-0
Horizontal Panel Size Bits [6:0]
This register determines the horizontal resolution of the panel. This register must be
programmed with a value calculated as follows:
Note: This register must not be set to a value less than 03h.
REG[03h] Mode Register 2
Address = 0x039FFE3
Read/Write
n/a
LCDPWR
Override
Hardware
Power Save
Enable
Software
Power Save Bit
1
Software
Power Save Bit
0
Table 5-5 Hardware Power Save/GPIO0 Operation
RESET#
State
Hardware Power
Save Enable
REG[03h] bit 2
GPIO0 Config
REG[18h] bit 0
GPIO0 Status/
Control
REG[19h] bit 0
GPIO0 Operation
0X
X
1
0
reads pin status
GPIO0 Input
(high impedance)
1
0
1
0
GPIO0 Output = 0
1
0
1
GPIO0 Output = 1
11
X
Hardware Power Save Input
(active high)
Table 5-6 Software Power Save Mode Selection
Bit 1
Bit 0
Mode
0
Software Power Save
0
1
reserved
1
0
reserved
1
Normal Operation
REG[04h] Horizontal Panel Size Register
Address = 0x039FFE4
Read/Write
n/a
Horizontal
Panel Size Bit
6
Horizontal
Panel Size Bit
5
Horizontal
Panel Size Bit
4
Horizontal
Panel Size Bit
3
Horizontal
Panel Size Bit
2
Horizontal
Panel Size Bit
1
Horizontal
Panel Size Bit
0
Horizontal Panel Size Register
Horizontal Panel Resolution (pixels)
8
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1
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