
5 REGISTERS
SID13705 HARDWARE FUNCTIONAL
EPSON
C-1-13
SPECIFICATION
REG[05h] bits 7-0
Vertical Panel Size Bits [9:0]
REG[06h] bits 1-0
This 10-bit register determines the vertical resolution of the panel. This reg-
ister must be programmed with a value calculated as follows.:
3FFh is the maximum value of this register for a vertical resolution of 1024
lines.
bits 4-0
FPLINE Start Position
These bits are used in TFT/D-TFD mode to specify the position of the FPLINE pulse.
These bits specify the delay, in 8-pixel resolution, from the end of a line of display data
(FPDAT) to the leading edge of FPLINE. This register is effective in TFT/D-TFD mode
only (REG[01h] bit 7 = 1). This register is programmed as follows:
The following constraint must be satisfied:
bits 4-0
Horizontal Non-Display Period
These bits specify the horizontal non-display period in 8-pixel resolution.
REG[05h] Vertical Panel Size Register (LSB)
Address = 0x039FFE5
Read/Write
Vertical Panel
Size
Bit 7
Vertical Panel
Size
Bit 6
Vertical Panel
Size
Bit 5
Vertical Panel
Size
Bit 4
Vertical Panel
Size
Bit 3
Vertical Panel
Size
Bit 2
Vertical Panel
Size
Bit 1
Vertical Panel
Size
Bit 0
REG[06h] Vertical Panel Size Register (MSB)
Address = 0x039FFE6
Read/Write
n/an/a
Vertical Panel
Size
Bit 9
Vertical Panel
Size
Bit 8
REG[07h] FPLINE Start Position
Address = 0x039FFE7
Read/Write
n/a
FPLINE Start
Position Bit 4
FPLINE Start
Position Bit 3
FPLINE Start
Position Bit 2
FPLINE Start
Position Bit 1
FPLINE Start
Position Bit 0
REG[08h] Horizontal Non-Display Period
Address = 0x039FFE8
Read/Write
n/a
Horizontal
Non-Display
Period Bit 4
Horizontal
Non-Display
Period Bit 3
Horizontal
Non-Display
Period Bit 2
Horizontal
Non-Display
Period Bit 1
Horizontal
Non-Display
Period Bit 0
Vertical Panel Size Register
Vertical Panel Resolution (lines)
1
–
=
FPLINEposition pixels
()
REG 07h
[] 2
+
() 8
×
=
REG 07h
[] REG 08h
[]
≤
Horizontal Non-Display Period (pixels)
REG 08h
[] 4
+
() 8
×
=