
III PERIPHERAL BLOCK: PRESCALER
S1C33L01 FUNCTION PART
EPSON
B-III-2-5
Name
Address
Register name
Bit
Function
Setting
Init.
R/W
Remarks
CLKDT1
CLKDT0
PSCON
–
CLKCHG
SOSC3
SOSC1
D7
D6
D5
D4–3
D2
D1
D0
System clock division ratio
selection
Prescaler On/Off control
reserved
CPU operating clock switch
High-speed (OSC3) oscillation On/Off
Low-speed (OSC1) oscillation On/Off
1 On
0 Off
1 OSC3
0 OSC1
1 On
0 Off
1 On
0 Off
0
1
0
1
R/W
–
R/W
Writing 1 not allowed.
0040180
(B)
1
0
1
0
1
0
CLKDT[1:0]
Division ratio
1/8
1/4
1/2
1/1
–
Power control
register
–
PSCDT0
D7–1
D0
reserved
Prescaler clock selection
0
–
R/W
0040181
(B)
–
Prescaler clock
select register
1 OSC1
0 OSC3/PLL
Writing 10010110 (0x96)
removes the write protection of
the power control register
(0x40180) and the clock option
register (0x40190).
Writing another value set the
write protection.
CLGP7
CLGP6
CLGP5
CLGP4
CLGP3
CLGP2
CLGP1
CLGP0
D7
D6
D5
D4
D3
D2
D1
D0
Power control register protect flag
0
R/W
004019E
(B)
Power control
protect register
PSCON: Prescaler on/off control (D5) / Power control register (0x40180)
Turns the prescaler on or off.
Write "1": On
Write "0": Off
Read: Valid
The source clock is input to the prescaler by writing "1" to PSCON, thereby starting a dividing operation.
The prescaler is turned off by writing "0". If the peripheral circuits do not need to be operated, write "0" to this bit to
reduce current consumption. Since PSCON is protected against writing the same as SOSC1, SOSC3, CLKCHG and
CLKDT[1:0], CLGP[7:0] must be set to "0b10010110" before PSCON can be changed.
At initial reset, PSCON is set to "1" (On).
CLGP7–CLGP0:Power-control register protection flag ([D[7:0]) / Power control protection register (0x4019E)
These bits remove the protection against writing to addresses 0x40180 and 0x40190.
Write "0b10010110": Write protection removed
Write other than the above: No operation (write-protected)
Read: Valid
Before writing to address 0x40180 or 0x40190, set CLGP[7:0] to "0b10010110" to remove the protection against
writing to that address. This clearing of write protection is effective for only one writing, so the bits are cleared to
"0b00000000" by one writing. Therefore, CLGP[7:0] must be set each time the protected address is written to.
At initial reset, CLGP is set to "0b00000000" (write-protected).
PSCDT0: Prescaler clock selection (D0) / Prescaler clock select register (0x40181)
Select the source clock for the prescaler.
Write "1": OSC1 clock
Write "0": OSC3 clock/PLL output clock
Read: Valid
When "1" is written to PSCDT0, the OSC1 clock (typ. 32 kHz) is selected.
When "0" is written, the OSC3 clock (when the PLL is not used) or the PLL output clock (when the PLL is used) is
selected.
For the prescaler clock, the clock source same as the CPU operating clock must be selected.
At initial reset, PSCDT0 is set to "0" (OSC3 clock/PLL output clock).