參數(shù)資料
型號： NAND01GW3B2CN1E
廠商： NUMONYX
元件分類： PROM
英文描述： 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù)： 8/65頁
文件大?。?/td> 1473K
代理商： NAND01GW3B2CN1E
Bus operations
NAND01G-B2C
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command input
Command input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal. For commands that start a modify operation (write/erase) the Write Protect pin must
be High.
Only I/O0 to I/O7 are used to input commands.
See Figure 20 and Table 24 for details of the timings requirements.
4.2
Address input
Address input bus operations are used to input the memory addresses. Four bus cycles are
required to input the addresses for 1-Gbit devices (refer to Table 6 and Table 7, Address
insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. For commands that start a modify operation (write/erase)
the Write Protect pin must be High. Only I/O0 to I/O7 are used to input addresses.
See Figure 21 and Table 24 for details of the timings requirements.
4.3
Data input
Data input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, Read Enable, and Write Protect is High. The data is latched on the
rising edge of the Write Enable signal. The data is input sequentially using the Write Enable
signal.
See Figure 22 and Table 24 and Table 25 for details of the timings requirements.
4.4
Data output
Data output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the unique identifier.
相關(guān)PDF資料
PDF描述
NAND04GR3B3AN6 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48
NAND512W3B3BZA1F 64M X 8 FLASH 3V PROM, 35 ns, PBGA63
NAND512W3B3CV1 64M X 8 FLASH 3V PROM, 35 ns, PDSO48
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NAND01GW4B3CZA1E 64M X 16 FLASH 3V PROM, 35 ns, PBGA63
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND01GW3B2CN1F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory
NAND01GW3B2CN6 制造商:STMicroelectronics 功能描述:128M X 8 FLASH 3V PROM, 35 ns, PDSO48
NAND01GW3B2CN6E 功能描述:IC FLASH 1GBIT 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
NAND01GW3B2CN6F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory
NAND01GW3B2CWFD 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
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