參數(shù)資料
型號: NAND01GW3B2CN1E
廠商: NUMONYX
元件分類: PROM
英文描述: 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48
封裝: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù): 31/65頁
文件大小: 1473K
代理商: NAND01GW3B2CN1E
NAND01G-B2C
Device operations
37/65
M
e
mo
ry
or
g
a
nizati
on
b
lo
c
k
80-83
M
Number of data bytes per page
84-85
M
Number of spare bytes per page
86-89
M
Number of data bytes per partial page
90-91
M
Number of spare bytes per partial page
92-95
M
Number of pages per block
96-99
M
Number of blocks per logical unit (LUN)
100
M
Number of logical units (LUNs)
101
M
Number of address cycles
Bit 4 to bit 7
Column address cycles
Bit 0 to bit 3
Row address cycles
102
M
Number of bits per cell
103-104
M
Bad blocks maximum per LUN
105-106
M
Block endurance
107
M
Guaranteed valid blocks at beginning of
target
108-109
M
Block endurance for guaranteed valid
blocks
110
M
Number of programs per page
111
M
Partial programming attributes
Bit 5 to bit 7
Reserved
4
1 = partial page layout is partial page
data followed by partial page spare
Bit 1 to bit 3
Reserved
0
1 = partial page programming has
constraints
112
M
Number of bits ECC correctability
113
M
Number of interleaved address bits
Bit 4 to bit 7
Reserved (0)
Bit 0 to bit 3
Number of interleaved address bits
114
O
Interleaved operation attributes
Bit 4 to bit 7
Reserved (0)
Bit 3
Address restrictions for program cache
Bit 2
1 = program cache supported
Bit 1
1 = no block address restrictions
Bit 0
Overlapped / concurrent interleaving
support
115-127
Reserved (0)
Table 16.
Parameter page data structure (continued)
Byte
O/M(1)
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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