參數(shù)資料
型號： NAND01GW3B2CN1E
廠商： NUMONYX
元件分類： PROM
英文描述： 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù)： 37/65頁
文件大?。?/td> 1473K
代理商： NAND01GW3B2CN1E
Software algorithms
NAND01G-B2C
8.3
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid. After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free area and the block containing the invalid pages is erased (see
8.4
Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate. Blocks with long-lived data do not endure as many write cycles as the blocks with
frequently-changed data.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
●
First level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
●
Second level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
8.5
Error correction code
Users must implement an error correction code (ECC) to identify and correct errors in data
stored in NAND flash memories. The ECC implemented must be able to correct 1 bit every
512 bytes. Sensible data stored in spare area must be covered by ECC as well.
8.6
Hardware simulation models
8.6.1
Behavioral simulation models
Denali Software Corporation models are platform independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND flash devices, and so allow
software to be developed before hardware.
8.6.2
IBIS simulation models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
相關(guān)PDF資料
PDF描述
NAND04GR3B3AN6 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48
NAND512W3B3BZA1F 64M X 8 FLASH 3V PROM, 35 ns, PBGA63
NAND512W3B3CV1 64M X 8 FLASH 3V PROM, 35 ns, PDSO48
NAND01GR4B3AV1F 64M X 16 FLASH 1.8V PROM, 35 ns, PDSO48
NAND01GW4B3CZA1E 64M X 16 FLASH 3V PROM, 35 ns, PBGA63
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND01GW3B2CN1F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory
NAND01GW3B2CN6 制造商:STMicroelectronics 功能描述:128M X 8 FLASH 3V PROM, 35 ns, PDSO48
NAND01GW3B2CN6E 功能描述:IC FLASH 1GBIT 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
NAND01GW3B2CN6F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory
NAND01GW3B2CWFD 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
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