參數(shù)資料
型號(hào)： NAND01GW3B2CN1E
廠商： NUMONYX
元件分類： PROM
英文描述： 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48
封裝： 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁(yè)數(shù)： 24/65頁(yè)
文件大小： 1473K
代理商： NAND01GW3B2CN1E
Device operations
NAND01G-B2C
6.6
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was performing when the command was
issued, refer to Table 25: AC characteristics for operations for the values.
6.7
Read status register
The device contains a status register which provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status register is read by issuing the Read Status Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore if a Read Status Register
command is issued during a random read cycle a new Read command must be issued to
continue with a page read operation.
The Status Register bits are summarized in Table 11: Status register bits,. Refer to Table 11
in conjunction with the following text descriptions.
6.7.1
Write protection bit (SR7)
The write protection bit can be used to identify if the device is protected or not. If the write
protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.7.2
P/E/R controller and cache ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation.
During cache read operations SR6 indicates whether the next selected page can be read
from the page register (SR6 is set to '1') or not (SR6 is set to '0').
During all other operations SR6 acts as a P/E/R controller bit, which indicates whether the
P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND01GW3B2CN1F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory
NAND01GW3B2CN6 制造商:STMicroelectronics 功能描述:128M X 8 FLASH 3V PROM, 35 ns, PDSO48
NAND01GW3B2CN6E 功能描述:IC FLASH 1GBIT 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
NAND01GW3B2CN6F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory
NAND01GW3B2CWFD 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
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