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參數(shù)資料
| 型號： | NAND01GW3B2CN1E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 21/65頁 |
| 文件大小： | 1473K |
| 代理商： | NAND01GW3B2CN1E |
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Device operations
NAND01G-B2C
6.4
Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back program operation fails, an error is signalled by the pass/fail status.
However, if copy back operations are accumulated over time, a bit error due to charge loss is
not checked by an external error detection/correction scheme. For this reason it is
recommended to use a 2-bit error correction in a copy back operation.
The copy back program operation requires four steps:
1.
The first step reads the source page. The operation copies all 1056 words/ 2112 bytes
from the page into the data buffer. It requires:
–
one bus write cycle to setup the command
–
–
one bus write cycle to issue the confirm command code
2.
When the device returns to the ready state (Ready/Busy High), the user may read the
contents of the source page by toggling R. In this case, random data output is also
allowed. To proceed with the copy back of the page into the target location, the user will
issue 85h followed by 4 bus cycles to input the target page address (see Table 6 and
3.
Then the confirm command is issued to start the P/E/R controller.
For an example of the copy back program operation, refer to Figure 12, while Figure 13
shows an example of Copy Back Program with Random Data Input.
A data input cycle to modify a portion or a multiple distant portion of the source page, is
shown in Figure 13.
Figure 12.
Copy back program
I/O
RB
Source
Add Inputs
ai09858b
85h
Copy Back
Code
Read
Code
Read Status Register
Target
Add Inputs
tBLBH1
(Read Busy time)
Busy
tBLBH2
(Program Busy time)
00h
10h
70h
SR0
Busy
35h
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| NAND04GR3B3AN6 | 512M X 8 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND512W3B3BZA1F | 64M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND512W3B3CV1 | 64M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND01GR4B3AV1F | 64M X 16 FLASH 1.8V PROM, 35 ns, PDSO48 |
| NAND01GW4B3CZA1E | 64M X 16 FLASH 3V PROM, 35 ns, PBGA63 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND01GW3B2CN1F | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory |
| NAND01GW3B2CN6 | 制造商:STMicroelectronics 功能描述:128M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND01GW3B2CN6E | 功能描述:IC FLASH 1GBIT 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| NAND01GW3B2CN6F | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1-Gbit, 2-Gbit, 2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory |
| NAND01GW3B2CWFD | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
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