參數(shù)資料
型號: NAND01GW3B2CN1E
廠商: NUMONYX
元件分類: PROM
英文描述: 128M X 8 FLASH 3V PROM, 25000 ns, PDSO48
封裝: 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48
文件頁數(shù): 22/65頁
文件大?。?/td> 1473K
代理商: NAND01GW3B2CN1E
NAND01G-B2C
Device operations
29/65
Figure 13.
Page copy back program with random data input
6.5
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to Figure 14):
1.
One bus cycle is required to setup the Block Erase command. Only addresses A18-
A27 (x8) or A17-A26 (x16) are used, the other address inputs are ignored
2.
Two bus cycles are then required to load the address of the block to be erased. Refer to
Table 8 and Table 9 for the block addresses of each device
3.
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
The operation is initiated on the rising edge of write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Figure 14.
Block erase operation
I/O
RB
Source
Add Inputs
ai11001
85h
Read
Code
Target
Add Inputs
tBLBH1
(Read Busy time)
00h
Busy
35h
85h
Data
2 Cycle
Add Inputs
Data
Copy Back
Code
10h
70h
Unlimited number of repetitions
Busy
tBLBH2
(Program Busy time)
SR0
I/O
RB
Block Address
Inputs
SR0
ai07593
D0h
70h
60h
Block Erase
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH3
(Erase Busy time)
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