
MOTOROLA
Chapter 3. Device Programming
3-3
Notes:
1. The MPC106 generates a memory select error (if enabled) for transactions in the address range
40000000–7FFFFFFF. If memory select errors are disabled, the MPC106 returns all 1s for read
operations and no update for write operations.
2. PCI configuration accesses to CF8 and CFC–CFF are handled as specified in the PCI Local Bus
Specification See Section 7.4.5, “Configuration Cycles,” for more information.
3. Processor addresses are translated to PCI addresses as follows:
In contiguous mode:
PCI address (AD[31–0]) = 0b0 || A[1–31]. PCI configuration accesses use processor addresses
80000CF8 and 80000CFC–80000CFF.
In discontiguous mode:
PCI address (AD[31–0]) = 0x0000 || A[9–19] || A[27–31]. PCI configuration accesses use
processor addresses 80067018 and 8006701C–8006701F.
4. IDSEL for direct-access method: 11=0x808008xx, 12=0x808010xx, ..., 18=0x808400xx.
5. Reads to this address generate PCI interrupt-acknowledge cycles; writes to this address generate TEA
(if enabled).
6. If the ROM is located on the PCI bus, these addresses are not reserved and PCI cycles will be
generated.
7. If the ISA_MASTER signal is asserted, the PCI memory cycle is forwarded to system memory and the
60x bus address becomes 0b00 || AD[29–0].
Table 3-3. Address Map A—PCI I/O Master View
PCI I/O Transactions Address Range
60x Address Range
Definition
Hex
Decimal
00000000
0000FFFF
0
64K – 1
No system memory cycle
ISA/PCI I/O space
00010000
007FFFFF
64K
8M – 1
No system memory cycle
Reserved
00800000
3F7FFFFF
8M
1G – 8M – 1
No system memory cycle
PCI I/O space
3F800000
3FFFFFFF
1G – 8M
1G – 1
No system memory cycle
Reserved
40000000
FFFFFFF
1G
4G – 1
No system memory cycle
Reserved