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MPC106 PCIB/MC User's Manual
MOTOROLA
3.2.4 Power Management Configuration Registers (PMCRs)
The power management configuration registers (PMCRs) control the power management
functions of the MPC106.
Power management configuration register 1 (PMCR1), shown in Figure 3-10, is a 2-byte
register located at offset 0x70. Some of the bits in PMCR1 configure the MPC106 to use
the distinct power management features of different 60x processors. Table 3-14 describes
the bits of PMCR1.
Figure 3-10. Power Management Configuration Register 1 (PMCR1)
Table 3-14. Bit Settings for Power Management Configuration
Register 1—0x70
Bit
Name
Reset
Value
Description
15
NO_NAP_MSG
0
HALT command broadcast
0
Indicates that the MPC106 broadcasts a HALT command onto
the PCI bus prior to entering the nap mode
1
Indicates that the MPC106 does not broadcast a HALT
command on the PCI bus prior to entering the nap mode
14
NO_SLEEP_MSG
0
Sleep message broadcast
0
Indicates that the MPC106 broadcasts a sleep message
command on the PCI bus prior to entering the sleep mode
1
Indicates that the MPC106 does not broadcast a sleep
message command on the PCI bus prior to entering the sleep
mode
The sleep message will be either a SHUTDOWN or HALT
command as determined by PMCR1[SLEEP_MSG_TYPE].
13
SLEEP_MSG_TYPE
0
Sleep message type
0
Indicates that the MPC106 broadcasts a HALT command onto
the PCI bus prior to entering the sleep mode
1
Indicates that the MPC106 broadcasts a SHUTDOWN
command onto the PCI bus prior to entering the sleep mode
Note that the sleep message will be broadcast only if
PMCR1[NO_SLEEP_MSG] = 0.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NO_NAP_MSG
SLEEP_MSG_TYPE
NO_SLEEP_MSG
LP_REF_EN
DOZE
NAP
SLEEP
CKO_MODE
NO_604_RUN
601_NEED_QREQ
BR1_WAKE
SUSP_QACK
0
0
Reserved
PM