MOTOROLA
Chapter 7. PCI Bus Interface
7-5
0110
Memory-read
Yes
Yes
The memory-read command accesses
either system memory, or agents mapped
into PCI memory space, depending on the
address. When a PCI master issues a
memory-read command to system memory,
the MPC106 (the target) fetches data from
the requested address to the end of the
cache line (32 bytes) from system memory,
even though all of the data may not be
requested by (or sent to) the master.
0111
Memory-write
Yes
Yes
The memory-write command accesses
either system memory, or agents mapped
into PCI memory space, depending on the
address.
1000
Reserved
*
No
No
—
1001
Reserved
*
No
No
—
1010
Configuration-read
Yes
No
The configuration-read command
accesses the 256-byte configuration space
of a PCI agent. A specific agent is selected
when its IDSEL signal is asserted during
the address phase. See Section 7.4.5,
“Configuration Cycles,” for more detail of
PCI configuration cycles.
1011
Configuration-write
Yes
No
The configuration-write command accesses
the 256-byte configuration space of a PCI
agent. A specific agent is selected when its
IDSEL signal is asserted during the address
phase. See Section 7.4.5.2, “Accessing the
PCI Configuration Space,” for more detail of
PCI configuration accesses.
1100
Memory-read-multiple
No
Yes
The memory-read-multiple command
functions similar to the memory-read
command, but it also causes a prefetch of
the next cache line (32 bytes).
Note that for PCI reads from system
memory, prefetching for all reads may be
forced by setting bit 2 (PCI speculative read
enable) of PICR1. See Section 8.1.3.1.1,
“Speculative PCI Reads from System
Memory,” for more information.
1101
Dual-address-cycle
No
No
The dual-address-cycle command is used
to transfer a 64-bit address (in two 32-bit
address cycles) to 64-bit addressable
devices. The MPC106 does not respond to
this command.
Table 7-1. PCI Bus Commands (Continued)
C/BE[3–0]
PCI Bus Command
MPC106
Supports
as a Master
MPC106
Supports
as a Target
Definition