
MOTOROLA
Glossary of Terms and Abbreviations
Glossary-5
(respectively) so that a subsequent operation can begin before the
previous one has completed.
Primary (L1) cache
. The cache resource that is most readily available to a
processor (for example, the internal cache of a 60x processor).
See
also
Secondary (L2) cache.
Retry.
Resending the current address or data beat until it can be accepted.
Refresh
. Periodic charging a device that cannot hold its content. Dynamic
RAM (DRAM) devices require refresh cycles every few
milliseconds to preserve their charged bit patterns.
Reservation
. The processor establishes a reservation on a
cache line
of
memory space when it executes an
lwarx
/
stwcx.
instruction to read
a memory semaphore into a GPR.
Reserved.
In a register, a reserved field is one that is not assigned a function.
A reserved field may be a single bit. The handling of reserved bits is
implementation-dependent. Software is permitted to write any value
to such a bit. A subsequent reading of the bit returns 0 if the value
last written to the bit was 0 and returns an undefined value (0 or 1)
otherwise.
RISC (reduced instruction set computing)
. An
architecture
characterized
by fixed-length instructions with nonoverlapping functionality and
by a separate set of load and store instructions that perform memory
accesses.
Scan interface
. The 60x’s test interface.
Secondary (L2) cache
.The cache resource that is next-to-the-most readily
available to a processor, the
primary (L1) cache
being the most
readily available. This cache is typically larger, offers slower access
time than a primary cache, and may be accessed by multiple devices.
The use of a secondary cache improves performance by reducing the
number of bus accesses to external main memory.
Set
(
v
). To write a nonzero value to a bit or bit field, the opposite of
clear
. The
term ‘set’ may also be used to generally describe the updating of a
bit or bit field.
Set
(
n
). A subdivision of a
cache
. Cacheable data can be stored in a given
location in any one of the sets, typically corresponding to its lower-
order address bits. Because several memory locations can map to the
R
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