MOTOROLA
Chapter 6. Memory Interface
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6.4.3 SDRAM Burst and Single-Beat Transactions
The MPC106 runs a burst-of-four for every transaction (burst and single-beat). For
single-beat read transactions, the MPC106 masks the extraneous data in the burst by driving
the DQM
n
signal high on the irrelevant cycles of the burst. For single-beat write
transactions, the MPC106 protects nontargeted addresses by driving the DQM
n
signal high
on the irrelevant cycles of the burst.
For single-beat transactions, the bursts cannot be terminated early. That is, if the relevant
data is in the first data phase, the subsequent data phases of the burst must run to completion
even though the data is irrelevant.
The MPC106 supports burst-of-four, double-word data beats for accesses to system
memory. The burst is always sequential, and the critical double word is always supplied
first. For example, if the 60x requests the third double word of a cache line, the MPC106
reads double words from memory in the order 2-3-0-1.
6.4.4 SDRAM Page Mode Retention
Under certain conditions, the MPC106 retains two active SDRAM pages for burst or
single-beat accesses. These conditions are:
A pending transaction (read or write) hits one of the currently active internal pages.
There are no pending refreshes.
The burst-to-precharge interval (controlled by BSTOPRE_U and BSTOPRE_L) has
not been exceeded.
The maximum activate-to-precharge interval (controlled by PGMAX) has not been
exceeded.
Page mode can dramatically reduce access latencies for page hits. Depending on the
memory system design and timing parameters, using page mode can save clock cycles from
subsequent burst accesses that hit in an active page. SDRAM page mode is controlled by
the BSTOPRE_U, BSTOPRE_L, and PGMAX parameters. Page mode is disabled by
clearing either BSTOPRE_U and BSTOPRE_L, or the PGMAX parameter.
The page open duration counter is loaded with BSTOPRE_U || BSTOPRE_L every time
the page is accessed (including page hits). When the counter expires (or when PGMAX
expires) the open page is closed with a precharge bank command. Page hits can occur at
any time in the interval specified by BSTOPRE.
The 1-byte memory page mode register at address offset 0xA3 contains the PGMAX
parameter that controls how long the MPC106 retains the currently accessed page (row) in
memory. The PGMAX parameter specifies the activate-to-precharge interval (sometimes
called row active time or t
RAS
). The PGMAX value is multiplied by 64 to generate the
actual number of clock cycles for the interval. When PGMAX is programmed to 0x00, page
mode is disabled.