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MC68MH360 Product Brief
D-6
MC68360 USER’S MANUAL
Figure D-3. Serial Channel to TDM Bus Implementation
Figure D-4 shows that the QUICC32 time-slot assigner can support two TDM buses. Each
TDM bus can be of a different format—for example, one TDM can be a T1 line, and one can
be a CEPT line. Also this technique could be used to bridge frames from basic rate ISDN to
a T1/CEPT line, etc.
The QUICC32 can route channels to and from the QMC protocol to the two different TDM
buses in any combination.
Figure D-4. Dual TDM Bus Implementation
Figure D-5 shows a TDM application having one line termination device that extracts clocks
and frame sychronization pulses. For T1/E1 line termination, devices exist that perform this
function. Alternatively, this can be achieved by a DSP from the Motorola 56K family.
For line termination the QUICC32 is capable of handling up to 32 channels and it may be
sufficient to omit the block labeled “Other PCM line devices”. If it is desired to incorporate
other PCM line devices in the system as shown in Figure D-5, the QUICC32 can provide
strobe signals to other devices that do not have a built-in time slot assigner.
QUICC
TIME DIVISION MULTIPLEXED BUS
T1, CEPT, IDL, GCI, ISDN,
PRIMARY RATE,
USER-DEFINED
TIME
SLOT
ASSIGNER
SCC
SMC
ANY COMBINATION OF SCCs
AND SMCs MAY BE
CONNECTED TO THE TDM.
NOTE: Independent receive and transmit clocking, routing,
and syncs are supported.
QUICC
TIME
SLOT
ASSIGNER
SCC
SMC
ANY COMBINATION OF SCCs
AND SMCs MAY BE
CONNECTED TO ANY TDM.
TDM BUS 1
TDM BUS 2
NOTE: Two TDM buses may be simultaneously supported
with the time slot assigner.
(E.g. 32 channels HDLC
(E.g. ISDN basic rate with
remaining SCC’s and SMC’s
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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