
Serial Communication Controllers (SCCs)
7-264
MC68360 USER’S MANUAL
7.10.23.20 ETHERNET EVENT REGISTER (SCCE). The SCCE is called the Ethernet
event register when the SCC is operating as an Ethernet controller. It is a 16-bit register
used to report events recognized by the Ethernet channel and to generate interrupts. On
recognition of an event, the Ethernet controller will set the corresponding bit in the Ethernet
event register. Interrupts generated by this register may be masked in the Ethernet mask
register. An example of interrupts that may be generated in the HDLC protocol is given in
Figure 7-72.
The Ethernet event register is a memory-mapped register that may be read at any time. A
bit is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
Bits 15–8, 6–5—Reserved
GRA—Graceful Stop Complete
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any frame
that was in progress when the command was issued. It will be set immediately if no frame
was in progress when the command was issued.
TXE—Tx Error
An error occurred on the transmitter channel.
RXF—Rx Frame
A complete frame was received on the Ethernet channel.
BSY—Busy Condition
A frame was received and discarded due to lack of buffers.
TXB—Tx Buffer
A buffer has been transmitted on the Ethernet channel.
RXB—Rx Buffer
A buffer that was not a complete frame has been received on the Ethernet channel.
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GRA
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TXE
RXF
BSY
TXB
RXB
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Freescale Semiconductor, Inc.
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