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CPU32+
MC68360 USER’S MANUAL
field allows the return-from-exception (RTE) instruction to identify what information is on the
stack so that it may be properly restored.
5.1.5 Addressing Modes
Addressing in the CPU32+ is register oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory; this flexibility elim-
inates the need for extra instructions to store register contents in memory.
The seven basic addressing modes are as follows:
Register Direct
Register Indirect
Register Indirect with Index
Program Counter Indirect with Displacement
Program Counter Indirect with Index
Absolute
Immediate
Included in the register indirect addressing modes are the capabilities to postincrement, pre-
decrement, and offset. The PC relative mode also has index and offset capabilities. In addi-
tion to these addressing modes, many instructions implicitly specify the use of the SR, SP
and/or PC. Addressing is explained fully in the M68000PM/AD,
M68000 Family Program-
mer’s Reference Manual.
5.2 ARCHITECTURE SUMMARY
The CPU32+ is upward source- and object-code compatible with the MC68000 and
MC68010. It is downward source- and object-code compatible with the MC68020. Within the
M68000 family, architectural differences are limited to the supervisory operating state. User
programs can be executed unchanged on upward-compatible devices.
The major CPU32+ features are as follows:
32-Bit Internal Data Path and Arithmetic Hardware
32-Bit Address Bus Supported by 32-Bit Calculations
Rich Instruction Set
Eight 32-Bit General-Purpose Data Registers
Seven 32-Bit General-Purpose Address Registers
Separate User and Supervisor Stack Pointers (USP and SSP)
Separate User and Supervisor Address Spaces
Separate Program and Data Address Spaces
Many Data Types
Flexible Addressing Modes
Full Interrupt Processing
Expansion Capability
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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