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System Integration Module (SIM60)
MC68360 USER’S MANUAL
MOVE
#7,D0
load D0 with the CPU space function code
MOVEC
D0,SFC
load SFC to indicate CPU space
MOVEC
D0,DFC
load DFC to indicate CPU space
LEA
$3FF00,A0
load A0 with the address of MBAR
MOVES.L
(A0),D0
load D0 with the contents of MBAR
MBAR can be written to using the following code. Address $0003FF00 in CPU space
(MBAR) will be loaded with the value $FFFF F001. This will set the base address of the inter-
nal registers to $FFFFF.
MOVE
#7,D0
load D0 with the CPU space function code
MOVEC
D0,SFC
load SFC to indicate CPU space
MOVEC
D0,DFC
load DFC to indicate CPU space
LEA
$3FF00,A0
load A0 with the address of MBAR
MOVE.L
#$FFFFF001,D0
load D0 with the value to be written into MBAR
MOVES.L
D0,(A0)
write the value contained in D0 into MBAR
6.9.2 Module Base Address Register Enable (MBARE)
The MBARE is a 32-bit, memory-mapped, read-write register. Upon a total system reset, its
value may be read as $0. The address of this register is fixed at $03FF08 in CPU space. It
is used to enable the MBAR to be programmed when multiple QUICCs are in slave mode.
CPU SPACE ONLY
MBS—MBAR Select
0 = No operation.
1 = The MBAR is now ready to be programmed on this slave QUICC device if the
MBARE pin was low during the write to this bit.
6.9.3 System Configuration and Protection Registers
The following paragraphs provide descriptions of the system configuration and protection
registers.
6.9.3.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the
SIM60 configuration, can be read or written at any time.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MBS
———————————————
RESET:
0
000000
000000000
15
14
13
12
11
10
9876543210
—
———————————————
RESET:
0
000000
000000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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