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型號：	MC68360FE25
廠商：	FREESCALE SEMICONDUCTOR INC
元件分類：	微控制器/微處理器
英文描述：	32-BIT, 25 MHz, RISC PROCESSOR, CQFP240
封裝：	CERAMIC, QFP-240
文件頁數：	56/962頁
文件大?。?/td>	26435K
代理商：	MC68360FE25

MC68360 USER’S MANUAL

Figure 5-4. Supervisor Programming Model Supplement

5.2.2 Registers

Registers D7–D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-

bit), and quad-word (64-bit) operations. Registers A6 to A0 and the USP and SSP are

address registers that may be used as software SPs or base address registers. Register A7

(shown as A7 and A7' in Figure 5-3 and Figure 5-4) is a register designation that applies to

the USP in the user privilege level and to the SSP in the supervisor privilege level. In addi-

tion, address registers may be used for word and long-word operations. All 16 general-pur-

pose registers (D7–D0, A7–A0) may be used as index registers.

The Program Counter (PC) contains the address of the next instruction to be executed by

the CPU32+. During instruction execution and exception processing, the processor auto-

matically increments the contents of the PC or places a new value in the PC, as appropriate.

The Status Register (SR) (see Figure 5-5) contains condition codes, an interrupt priority

mask (three bits), and three control bits. Condition codes reflect the results of a previous

operation. The codes are contained in the low byte (CCR) of the SR. The interrupt priority

mask determines the level of priority an interrupt must have to be acknowledged. The control

bits determine trace mode and privilege level. At user privilege level, only the CCR is avail-

able. At supervisor privilege level, software can access the full SR.

The Vector Base Register (VBR) contains the base address of the exception vector table in

memory. The displacement of an exception vector is added to the value in this register to

access the vector table.

Alternate source and destination function code registers (SFC and DFC) contain 3-bit func-

tion codes. The CPU32+ generates a function code each time it accesses an address. Spe-

cific codes are assigned to each type of access. The codes can be used to select eight

dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and

DFC to specify the function code of a memory address.

SUPERVISOR STACK

STATUS REGISTER

FUNCTION CODE

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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