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Signal Descriptions
2-2
MC68360 USER’S MANUAL
NOTE
Write enable does not have the capability to follow dynamic bus
sizing with external assertion of DSACK. Write enable will al-
ways follow the port size that is programed in GMR and the OR.
For more information see 6.10 Memory Controller.
Figure 2-1. QUICC Functional Signal Groups
D31–D16
ADDRESS BUS
BUS CONTROL
BUS ARBITRATION
SYSTEM CONTROL
INTERRUPT CONTROL
TEST
CLOCK
TXD1/PA1
BRGCLK1/TOUT1/CLK2/PA9
PORT B (PIP)
TIMERs/SCCs/SIs/CLOCKs/BRG
MEMORY CONTROLLER
PORT A
RXD1/PA0
RXD2/PA2
TXD2/PA3
L1TXDB/RXD3/PA4
L1RXDB/TXD3/PA5
L1TXDA/RXD4/PA6
L1RXDA/TXD4/PA7
TIN1/L1RCLKA/BRGO1/CLK1/PA8
TIN2/L1TCLKA/BRGO2/CLK3/PA10
TOUT2/CLK4/PA11
TIN3/BRGO3/CLK5/PA12
BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13
TIN4/BRGO4/CLK7/PA14
L1TCLKB/TOUT4/CLK8/PA15
RRJCT1/SPISEL/PB0
RSTRT2/SPICLK/PB1
RRJCT2/SPIMOSI(SPITXD)/PB2
BRGO4/SPIMISO(SPIRXD)/PB3
DREQ1/BRGO1/PB4
DACK1/BRGO2/PB5
DONE1/SMTXD1/PB6
DONE2/SMRXD1/PB7
DREQ2/SMSYN1/PB8
DACK2/SMSYN2/PB9
L1CLKOB/SMTXD2/PB10
L1CLKOA/SMRXD2/PB11
L1ST1/RTS1/PB12
L1ST2/RTS2/PB13
L1ST3/L1RQB/RTS3/PB14
L1ST4/L1RQA/RTS4/PB15
STRBO/BRGO3/PB16
STRBI/RSTRT1/PB17
L1ST1/RTS1/PC0
L1ST2/RTS2/PC1
L1ST3/L1RQB/RTS3/PC2
L1ST4/L1RQA/RTS4/PC3
CTS1/PC4
TGATE1/CD1/PC5
CTS2/PC6
TGATE2/CD2/PC7
SDACK2/L1TSYNCB/CTS3/PC8
L1RSYNCB/CD3/PC9
SDACK1/L1TSYNCA/CTS4/PC10
L1RSYNCA/CD4/PC11
PORT C (INTERRUPT PARALLEL I/O)
CLKO2–CLKO1
MODCK1–MODCK0
XFC
EXTAL
XTAL
TRST
TDO
TDI
TMS
TCK
IFETCH/BADD3/DSI
IPIPE0/BADD2/DSO
IPIPE1/RAS1DD/BCLRI
FREEZE/CONFIG2/MBARE
BKPT/BKPTO/DSCLK
TRIS/TS
CAS3–CAS0/IACK6,3,2,1
CS/RAS7/IACK7
CS6–CS0/RAS6–RAS0
AVEC/IACK5/AVECO
IRQ2,3,5,7
IRQ6/IOUT2
IRQ4/IOUT1
IRQ1/IOUT0/RQOUT
PERR
BERR/TEA
HALT
RESETS
RESETH
BCLRO/CONFIG1/RAS2DD
BGACK/BB
BG
BR
RMC/CONFIG0/LOCK
OE/AMUX
DS/TT1
AS
R/W
DSACK1/TA
DSACK0/TBI
SIZ1
SIZ0
DATA BUS
PRTY3/16BM
PRTY2/IOUT0/RQOUT
D15–D0
PRTY1–PRTY0/IOUT1–IOUT2
A27–A0
A31–A28/WE3–WE0
FC2–FC0/TM2–TM0
FC3/TT0
QUICC
MC68360
240 PINS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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