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System Integration Module (SIM60)
MC68360 USER’S MANUAL
NOTES
This mode is used in QUICC slave operation to assert either the
BKPTO line for the external CPU or the internal IMB BKPT line
for an internal-to-internal IDMA/SDMA access. When the exter-
nal bus is used, the breakpoint line will be asserted as if the
SIZM bit is set.
In the case of an external MC68040 burst, only the first address
of the burst is checked.
When the QUICC is in master mode this bit should be zero to
prevent external breakpoint from being ignored.
RW1–RW0—Read/Write Selection
Assert a breakpoint match on read cycles only, write cycles only, or on both.
00 = Assert breakpoint on read cycles.
01 = Assert breakpoint on write cycles.
10 = Assert breakpoint on read or write cycles.
11 = Reserved.
SIZM—Size Mask
This bit determines whether the breakpoint logic will use the SIZ bits to determine whether
a breakpoint match has occurred.
0 = Compare the size lines as programmed in the SIZ bits to determine whether a
breakpoint match has occurred.
NOTE
This mode would normally be used to break on an access to a
location that contains data.
1 = Mask the size lines. The size of the access is not used in determining whether a
breakpoint match has occurred. The breakpoint logic will assert the break signal
when the address and size overlaps the programmable value. For example if the
programmable address is xxx2, the breakpoint line for the low word will be asserted
when the access address is xxx2 with a word size or when the address is xxx0 with
a long-word size.
NOTE
This mode would normally be used to break on an instruction
fetch.
SIZ1–SIZ10—Size Bits
The breakpoint logic can cause a breakpoint match for accesses that correspond to the
size of the access. Set the SIZM bit to disable this feature.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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