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Serial Management Controllers (SMCs)
MC68360 USER’S MANUAL
Refer to Figure 7-73 for the SMC block diagram. The SMC receiver and transmitter are dou-
ble-buffered, as shown in the block diagram. This corresponds to an effective FIFO size
(latency) of two characters.
Figure 7-73. SMC Block Diagram
The receive data source for an SMC can be either the L1RXD pin if the SMC is connected
to a TDM channel of the SI, or the SMRXD pin if the SMC is connected to the NMSI. The
transmit data source can either be the L1TXD pin if the SMC is connected to a TDM, or the
SMTXD pin if the SMC is connected to the NMSI.
If the SMC is connected to a TDM, the SMC receive clock and SMC transmit clock can be
independent from each other as defined in the SI description. However, if the SMC is con-
nected to the NMSI, the SMC receive clock and SMC transmit clock must be connected to
a single clock source called SMCLK. SMCLK is an internal signal name for a clock that is
generated from the bank of clocks defined in the SI description. SMCLK may originate from
an external pin or one of the four internal baud rate generators. See 7.8.9 NMSI Configura-
tion for more details.
If the SMC is connected to a TDM, it derives its synchronization pulse from the TSA as
defined in the SI description. Otherwise, if the SMC is connected to the NMSI and the totally
transparent protocol is selected, the SMC may use the SMSYN pin as a synchronization pin
to determine when transmission and reception should begin. (The SMSYN pin is not used
in the SMC UART mode.)
RECEIVER
SER TO PAR
TRANSMITTER
PAR TO SER
MODE _REGISTER
PERIPHERAL BUS
IMB
CONTROL
TX CLOCK
RX CLOCK
RX DATA
TX DATA
R_ DATA_ REGISTER
T_ DATA_ REGISTER
FROM L1RXD IN SI OR SMRXD
TO L1TXD IN SI OR SMTXD
SYNC
FROM SI OR SMSYN
FROM SI OR SMCLK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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