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Dual-Port RAM
MC68360 USER’S MANUAL
Figure 7-3. Dual-Port RAM Block Diagram
The dual-port RAM can be accessed by the RISC or one of four bus masters: CPU32+ core,
IDMAs, SDMAs, or external bus master. When the dual-port RAM is accessed by an exter-
nal bus master, CPU32+ core, IDMA, or SDMA channel, it is accessed in three clocks. When
the dual-port RAM is accessed by the RISC, it is accessed in one clock. In the case of simul-
taneous access (with at least one write operation), the RISC is delayed by one clock.
When the dual-port RAM is accessed by the CPU32+ core, IDMAs, SDMAs, or external bus
master, the data and address are taken from the IMB. The data is then presented on the IMB
data bus. The RISC has access to the entire dual-port RAM for data fetches and portions of
the system RAM for microcode instruction fetches.
The dual-port RAM is used for five possible tasks; any two tasks can occur simultaneously.
The first use is to store parameters associated with the SCCs, SMCs, SPI, and IDMAs in the
768-byte parameter RAM. The second use is to store the buffer descriptors that describe
where data is to be received and transmitted from. The third use is to store data from the
serial channels. This usage is optional since data may also be stored externally in the sys-
tem memory. The fourth use is to store RAM microcode for the RISC processor. This feature
allows additional protocols to be added by Motorola in the future. The fifth use is for addi-
tional scratchpad RAM space for the user program.
SYSTEM
RAM
1792 BYTES
PARMETER
RAM
768 BYTES
CP MICROCODE
ADDRESS
IMB
ADDRESS
BUS
CP MICROCODE DATA
IMB
DATA BUS
512
BYTES
256
BYTES
512
BYTES
512
BYTES
ADDRESS
SELECTOR
PERIPHERAL
DATA BUS
ADDRESS
SELECTOR
INTERNAL
PERIPHERAL
ADDRESS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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