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CPU32+
5-68
MC68360 USER’S MANUAL
BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the
assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32+ as the first
DSCLK.
DSCLK, the gated serial clock, is normally high, but it pulses low for each bit to be trans-
ferred. At the end of the seventeenth clock period, it remains high until the start of the next
transmission. Clock frequency is implementation dependent and may range from DC to the
maximum specified frequency. Although performance considerations might dictate a hard-
ware implementation, software solutions can be used provided serial bus timing is main-
tained.
5.6.2.8 COMMAND SET. The following paragraphs describe the command set available in
BDM.
5.6.2.8.1 Command Format. The following standard bit .command format is utilized by all
BDM commands.
Bits 15–10—Operation Field
The operation field specifies the commands. This 6-bit field provides for a maximum of 64
unique commands.
R/W Field
The R/W field specifies the direction of operand transfer. When the bit is set, the transfer
is from theCPU to the development system. When the bit is cleared, data is written to the
CPU or to memory from the development system.
Operand Size
For sized operations, this field specifies the operand data size. All addresses are ex-
pressed as 32-bit absolute values. The size field is encoded as listed in
Table 5-22..Address/Data (A/D) Field
The A/D field is used by commands that operate on address and data registers. It deter-
mines whether the register field specifies a data or address register. One indicates an ad-
dress register; zero indicates a data register. For other commands, this field may be
interpreted differently.
15
10
98765432
0
OPERATION
0
R/W
OP SIZE
0
A/D
REGISTER
EXTENSION WORD(S)
Table 5-22. Size Field Encoding
Encoding
Operand Size
00
Byte
01
Word
10
Long
11
Reserved
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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